From 7a50e786214f67f751f8b6cbd44920bb5d11e4d0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Amaury=20S=C3=A9chet?= Date: Wed, 14 Jun 2023 21:17:40 +0000 Subject: [PATCH] [NFC] Autogenerate various Thumb2 tests. --- ...2013-03-02-vduplane-nonconstant-source-index.ll | 24 ++++++++++--- llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll | 39 +++++++++++++--------- 2 files changed, 43 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll b/llvm/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll index 779b5c0..693c11a 100644 --- a/llvm/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll +++ b/llvm/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll @@ -1,10 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s define void @bar(ptr %p, i32 %lane, <4 x i32> %phitmp) nounwind { -; CHECK: lsls r[[ADDR:[0-9]+]], r[[ADDR]], #2 -; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128], r[[ADDR]] -; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[SOURCE]]:32] -; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0] +; CHECK-LABEL: bar: +; CHECK: @ %bb.0: +; CHECK-NEXT: push {r4, r7, lr} +; CHECK-NEXT: add r7, sp, #4 +; CHECK-NEXT: sub sp, #20 +; CHECK-NEXT: mov r4, sp +; CHECK-NEXT: bfc r4, #0, #4 +; CHECK-NEXT: mov sp, r4 +; CHECK-NEXT: and r1, r1, #3 +; CHECK-NEXT: vldr d17, [r7, #8] +; CHECK-NEXT: vmov d16, r2, r3 +; CHECK-NEXT: mov r2, sp +; CHECK-NEXT: lsls r1, r1, #2 +; CHECK-NEXT: subs r4, r7, #4 +; CHECK-NEXT: vst1.64 {d16, d17}, [r2:128], r1 +; CHECK-NEXT: vld1.32 {d16[], d17[]}, [r2:32] +; CHECK-NEXT: vst1.32 {d16, d17}, [r0] +; CHECK-NEXT: mov sp, r4 +; CHECK-NEXT: pop {r4, r7, pc} %val = extractelement <4 x i32> %phitmp, i32 %lane %r1 = insertelement <4 x i32> undef, i32 %val, i32 1 %r2 = insertelement <4 x i32> %r1, i32 %val, i32 2 diff --git a/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll b/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll index b667b53..ed0dcdf 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -1,12 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { -; CHECK: t1 -; CHECK: mov r0, r1 -; CHECK: mvn r1, #-2147483648 -; CHECK: cmp r2, #10 -; CHECK: it le -; CHECK: addle r0, r1 +; CHECK-LABEL: t1: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: mvn r1, #-2147483648 +; CHECK-NEXT: cmp r2, #10 +; CHECK-NEXT: it le +; CHECK-NEXT: addle r0, r1 +; CHECK-NEXT: bx lr %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 %tmp3 = add i32 %tmp2, %b @@ -14,11 +17,13 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { } define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { -; CHECK: t2 -; CHECK: mov r0, r1 -; CHECK: cmp r2, #10 -; CHECK: it le -; CHECK: addle.w r0, r0, #-2147483648 +; CHECK-LABEL: t2: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: cmp r2, #10 +; CHECK-NEXT: it le +; CHECK-NEXT: addle.w r0, r0, #-2147483648 +; CHECK-NEXT: bx lr %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483648 @@ -27,11 +32,13 @@ define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { } define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { -; CHECK: t3 -; CHECK: mov r0, r1 -; CHECK: cmp r2, #10 -; CHECK: it le -; CHECK: suble r0, #10 +; CHECK-LABEL: t3: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: cmp r2, #10 +; CHECK-NEXT: it le +; CHECK-NEXT: suble r0, #10 +; CHECK-NEXT: bx lr %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 10 %tmp3 = sub i32 %b, %tmp2 -- 2.7.4