From 7a38618a20596e419abbbbb249300e812763a028 Mon Sep 17 00:00:00 2001 From: Daniel Kiss Date: Tue, 9 Jun 2020 19:56:30 +0200 Subject: [PATCH] [AArch64] Allow BTI mnemonics in the HINT space with BTI disabled Summary: It is important to emit HINT instructions instead of BTI ones when BTI is disabled. This allows compatibility with other assemblers (e.g. GAS). Still, developers of assembly code will want to write code that is compatible with both pre- and post-BTI CPUs. They could use HINT mnemonics, but the new mnemonics are a lot more readable (e.g. bti c instead of hint #34), and they will result in the same encodings. So, while LLVM should not *emit* the new mnemonics when BTI is disabled, this patch will at least make LLVM *accept* assembly code that uses them. Reviewers: pbarrio, tamas.petz, ostannard Reviewed By: pbarrio, ostannard Subscribers: ostannard, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81257 --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 ++++++ llvm/test/MC/AArch64/armv8.5a-bti.s | 18 +++++++----------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index d642640..5aa7376 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -726,6 +726,12 @@ def : InstAlias<"sevl", (HINT 0b101)>; def : InstAlias<"dgh", (HINT 0b110)>; def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; def : InstAlias<"csdb", (HINT 20)>; +// In order to be able to write readable assembly, LLVM should accept assembly +// inputs that use Branch Target Indentification mnemonics, even with BTI disabled. +// However, in order to be compatible with other assemblers (e.g. GAS), LLVM +// should not emit these mnemonics unless BTI is enabled. +def : InstAlias<"bti", (HINT 32), 0>; +def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>; def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>; def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>; diff --git a/llvm/test/MC/AArch64/armv8.5a-bti.s b/llvm/test/MC/AArch64/armv8.5a-bti.s index ca55516..e0585f7 100644 --- a/llvm/test/MC/AArch64/armv8.5a-bti.s +++ b/llvm/test/MC/AArch64/armv8.5a-bti.s @@ -1,6 +1,6 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+bti < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-bti < %s 2>&1 | FileCheck %s --check-prefix=NOBTI +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+bti < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-bti < %s | FileCheck %s --check-prefix=NOBTI bti bti c @@ -12,14 +12,10 @@ bti jc // CHECK: bti j // encoding: [0x9f,0x24,0x03,0xd5] // CHECK: bti jc // encoding: [0xdf,0x24,0x03,0xd5] -// NOBTI: instruction requires: bti -// NOBTI-NEXT: bti -// NOBTI: instruction requires: bti -// NOBTI-NEXT: bti -// NOBTI: instruction requires: bti -// NOBTI-NEXT: bti -// NOBTI: instruction requires: bti -// NOBTI-NEXT: bti +// NOBTI: hint #32 // encoding: [0x1f,0x24,0x03,0xd5] +// NOBTI: hint #34 // encoding: [0x5f,0x24,0x03,0xd5] +// NOBTI: hint #36 // encoding: [0x9f,0x24,0x03,0xd5] +// NOBTI: hint #38 // encoding: [0xdf,0x24,0x03,0xd5] hint #32 hint #34 -- 2.7.4