From 7a275dc35411b8c3f510166f40c225cd10dc5eec Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 20 Jan 2022 11:49:35 -0800 Subject: [PATCH] [RISCV] Remove Zvlsseg extension. This string no longer appears in the Vector Extension specification. The segment load/store instructions are just part of the vector instruction set. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D117724 --- clang/include/clang/Basic/RISCVVTypes.def | 4 +- clang/include/clang/Basic/riscv_vector.td | 6 +- .../RISCV/rvv-intrinsics-overloaded/vloxseg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vlseg.c | 4 +- .../RISCV/rvv-intrinsics-overloaded/vlsegff.c | 4 +- .../RISCV/rvv-intrinsics-overloaded/vlsseg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vluxseg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vsoxseg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vsseg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vssseg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vsuxseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c | 4 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c | 4 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c | 2 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c | 2 +- clang/test/Driver/riscv-arch.c | 19 - clang/test/Preprocessor/riscv-target-features.c | 2 - clang/utils/TableGen/RISCVVEmitter.cpp | 11 +- llvm/lib/Support/RISCVISAInfo.cpp | 13 +- llvm/lib/Target/RISCV/RISCV.td | 10 +- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 12 +- llvm/lib/Target/RISCV/RISCVSchedRocket.td | 2 +- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 2 +- llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 - llvm/test/CodeGen/RISCV/attributes.ll | 12 +- llvm/test/MC/RISCV/attribute-arch-invalid.s | 4 +- llvm/test/MC/RISCV/attribute-arch.s | 40 +- llvm/test/MC/RISCV/rvv/zvlsseg.s | 1018 ++++++++++---------- 33 files changed, 576 insertions(+), 625 deletions(-) diff --git a/clang/include/clang/Basic/RISCVVTypes.def b/clang/include/clang/Basic/RISCVVTypes.def index f6ef62a..1d4024d 100644 --- a/clang/include/clang/Basic/RISCVVTypes.def +++ b/clang/include/clang/Basic/RISCVVTypes.def @@ -30,8 +30,8 @@ // // - ElBits is the size of one element in bits (SEW). // -// - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions -// (TODO). +// - NF is the number of fields (NFIELDS) used in the Load/Store Segment +// instructions (TODO). // // - IsSigned is true for vectors of signed integer elements and // for vectors of floating-point elements. diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 03e16be..28c57cc 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -215,10 +215,10 @@ class RVVBuiltin RequiredExtensions = []; - // Number of fields for Zvlsseg. + // Number of fields for Load/Store Segment instructions. int NF = 1; } @@ -1567,7 +1567,6 @@ defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>; defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>; // 7.8 Vector Load/Store Segment Instructions -let RequiredExtensions = ["Zvlsseg"] in { defm : RVVUnitStridedSegLoad<"vlseg">; defm : RVVUnitStridedSegLoadFF<"vlseg">; defm : RVVStridedSegLoad<"vlsseg">; @@ -1577,7 +1576,6 @@ defm : RVVUnitStridedSegStore<"vsseg">; defm : RVVStridedSegStore<"vssseg">; defm : RVVIndexedSegStore<"vsuxseg">; defm : RVVIndexedSegStore<"vsoxseg">; -} // 12. Vector Integer Arithmetic Instructions // 12.1. Vector Single-Width Integer Add and Subtract diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c index 9cb3325..0df229d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c index a0f04dc..ac49608 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c @@ -2,12 +2,12 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c index f2b9e44..22df2b9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c @@ -2,12 +2,12 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c index 82c4c57..4f79022 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c index a2dbaaf..8db5e80 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c index 5f41c6b..d3454be 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c index 662ee6b..b727219 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c index 8952c2d..2a95d46 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c index f6bfd78..3a338ad 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c index 41f4f69..f278bb7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c index 11cd459..deaaf0e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c @@ -2,12 +2,12 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c index 20a7965..fba2c17 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c @@ -2,12 +2,12 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -target-feature +zfh \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ +// RUN: -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c index 5584d84..cfdf827 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c index bd499de..b83ff98 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c index 03b8667..ac8c4a4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c index 6f3927c..0829100 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c index 488a93c..b91c023 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c index aa55916..a6bdc1a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +zfh -target-feature +experimental-v \ -// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ +// RUN: -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index c81a87c..656abde 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -416,25 +416,6 @@ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v" -// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -### %s -c 2>&1 | \ -// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s -// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32iv0p10_zvlsseg' -// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions' - -// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \ -// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s -// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32iv0p10_zvlsseg' -// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit version number - -// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \ -// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s -// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32iv0p10_zvlsseg0p1' -// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg' - -// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ -// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s -// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg" - // RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s // RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv0p10_zvl32b0p10' diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index ba31022..c69285f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -31,7 +31,6 @@ // CHECK-NOT: __riscv_zfh // CHECK-NOT: __riscv_v // CHECK-NOT: __riscv_vector -// CHECK-NOT: __riscv_zvlsseg // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s @@ -220,7 +219,6 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s // CHECK-V-EXT: __riscv_v 10000{{$}} // CHECK-V-EXT: __riscv_vector 1 -// CHECK-V-EXT: __riscv_zvlsseg 10000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu \ // RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \ diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index d3f1d631..84da6a5 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -140,8 +140,7 @@ enum RISCVExtension : uint8_t { F = 1 << 1, D = 1 << 2, Zfh = 1 << 3, - Zvlsseg = 1 << 4, - RV64 = 1 << 5, + RV64 = 1 << 4, }; // TODO refactor RVVIntrinsic class design after support all intrinsic @@ -445,8 +444,8 @@ void RVVType::initBuiltinStr() { return; } BuiltinStr = "q" + utostr(Scale.getValue()) + BuiltinStr; - // Pointer to vector types. Defined for Zvlsseg load intrinsics. - // Zvlsseg load intrinsics have pointer type arguments to store the loaded + // Pointer to vector types. Defined for segment load intrinsics. + // segment load intrinsics have pointer type arguments to store the loaded // vector values. if (IsPointer) BuiltinStr += "*"; @@ -797,8 +796,6 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, RISCVExtensions |= RISCVExtension::D; } for (auto Extension : RequiredExtensions) { - if (Extension == "Zvlsseg") - RISCVExtensions |= RISCVExtension::Zvlsseg; if (Extension == "RV64") RISCVExtensions |= RISCVExtension::RV64; } @@ -1311,8 +1308,6 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) { OS << LS << "defined(__riscv_d)"; if (Extents & RISCVExtension::Zfh) OS << LS << "defined(__riscv_zfh)"; - if (Extents & RISCVExtension::Zvlsseg) - OS << LS << "defined(__riscv_zvlsseg)"; if (Extents & RISCVExtension::RV64) OS << LS << "(__riscv_xlen == 64)"; OS << "\n"; diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index d1d222d..fc52fc6 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -66,7 +66,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zbr", RISCVExtensionVersion{0, 93}}, {"zbt", RISCVExtensionVersion{0, 93}}, - {"zvlsseg", RISCVExtensionVersion{0, 10}}, {"zvl32b", RISCVExtensionVersion{0, 10}}, {"zvl64b", RISCVExtensionVersion{0, 10}}, {"zvl128b", RISCVExtensionVersion{0, 10}}, @@ -301,9 +300,7 @@ void RISCVISAInfo::toFeatures( if (ExtName == "i") continue; - if (ExtName == "zvlsseg") { - Features.push_back("+experimental-zvlsseg"); - } else if (isExperimentalExtension(ExtName)) { + if (isExperimentalExtension(ExtName)) { Features.push_back(StrAlloc("+experimental-" + ExtName)); } else { Features.push_back(StrAlloc("+" + ExtName)); @@ -691,7 +688,6 @@ Error RISCVISAInfo::checkDependency() { bool HasE = Exts.count("e") == 1; bool HasD = Exts.count("d") == 1; bool HasF = Exts.count("f") == 1; - bool HasZvlsseg = Exts.count("zvlsseg") == 1; bool HasVector = Exts.count("zve32x") == 1; bool HasZve32f = Exts.count("zve32f") == 1; bool HasZve64d = Exts.count("zve64d") == 1; @@ -710,11 +706,6 @@ Error RISCVISAInfo::checkDependency() { return createStringError(errc::invalid_argument, "d requires f extension to also be specified"); - if (HasZvlsseg && !HasVector) - return createStringError( - errc::invalid_argument, - "zvlsseg requires v or zve* extension to also be specified"); - // FIXME: Consider Zfinx in the future if (HasZve32f && !HasF) return createStringError( @@ -745,7 +736,7 @@ static const char *ImpliedExtsZve64d[] = {"zve64f"}; static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; static const char *ImpliedExtsZve32f[] = {"zve32x"}; -static const char *ImpliedExtsZve32x[] = {"zvlsseg", "zvl32b"}; +static const char *ImpliedExtsZve32x[] = {"zvl32b"}; static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"}; static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"}; static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"}; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index fda400e..36c7263 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -161,19 +161,11 @@ foreach i = { 6-15 } in { [!cast("FeatureStdExtZvl"#!srl(I, 1)#"b")]>; } -def FeatureStdExtZvlsseg - : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", - "'Zvlsseg' (Vector segment load/store instructions)", - []>; -def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, - AssemblerPredicate<(all_of FeatureStdExtZvlsseg), - "'Zvlsseg' (Vector segment load/store instructions)">; - def FeatureStdExtZve32x : SubtargetFeature<"experimental-zve32x", "HasStdExtZve32x", "true", "'Zve32x' (Vector Extensions for Embedded Processors " "with maximal 32 EEW)", - [FeatureStdExtZvlsseg, FeatureStdExtZvl32b]>; + [FeatureStdExtZvl32b]>; def HasStdExtZve32x : Predicate<"SubTarget->hasStdExtZve32x()">, AssemblerPredicate<(all_of FeatureStdExtZve32x), "'Zve32x' (Vector Extensions for Embedded Processors " diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index afdd7c4..306024a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1461,7 +1461,7 @@ foreach n = [2, 4, 8] in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVInstructions] -let Predicates = [HasStdExtZvlsseg] in { +let Predicates = [HasVInstructions] in { foreach nf=2-8 in { foreach eew = [8, 16, 32] in { defvar w = !cast("LSWidth"#eew); @@ -1494,9 +1494,9 @@ let Predicates = [HasStdExtZvlsseg] in { "vsoxseg"#nf#"ei"#eew#".v">; } } -} // Predicates = [HasStdExtZvlsseg] +} // Predicates = [HasVInstructions] -let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in { +let Predicates = [HasVInstructionsI64] in { foreach nf=2-8 in { // Vector Unit-strided Segment Instructions def VLSEG#nf#E64_V : @@ -1512,8 +1512,8 @@ let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in { def VSSSEG#nf#E64_V : VStridedSegmentStore; } -} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] -let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in { +} // Predicates = [HasVInstructionsI64] +let Predicates = [HasVInstructionsI64, IsRV64] in { foreach nf=2-8 in { // Vector Indexed Segment Instructions def VLUXSEG#nf#EI64_V : @@ -1529,6 +1529,6 @@ let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in { VIndexedSegmentStore; } -} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] +} // Predicates = [HasVInstructionsI64, IsRV64] include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index 2d80d9d..4655015 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel { let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = false; - let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64]; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index b39082f..3b3e269 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel { let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = 0; - let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtV]; } // The SiFive7 microarchitecture has two pipelines: A and B. diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index f8eb8e0..d55affd 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -81,7 +81,6 @@ private: bool HasStdExtZve64x = false; bool HasStdExtZve64f = false; bool HasStdExtZve64d = false; - bool HasStdExtZvlsseg = false; bool HasStdExtZfhmin = false; bool HasStdExtZfh = false; bool HasRV64 = false; @@ -160,7 +159,6 @@ public: bool hasStdExtZve64x() const { return HasStdExtZve64x; } bool hasStdExtZve64f() const { return HasStdExtZve64f; } bool hasStdExtZve64d() const { return HasStdExtZve64d; } - bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } bool hasStdExtZfh() const { return HasStdExtZfh; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index f04eb26..59790c9 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -18,7 +18,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s -; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s +; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s @@ -37,7 +37,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s -; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s +; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" @@ -57,8 +57,8 @@ ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" +; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0" @@ -77,8 +77,8 @@ ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" -; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" +; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch-invalid.s b/llvm/test/MC/RISCV/attribute-arch-invalid.s index 933de29..1dd5621 100644 --- a/llvm/test/MC/RISCV/attribute-arch-invalid.s +++ b/llvm/test/MC/RISCV/attribute-arch-invalid.s @@ -26,5 +26,5 @@ .attribute arch, "rv32izbt" # CHECK: error: invalid arch name 'rv32izbt', experimental extension requires explicit version number `zbt` -.attribute arch, "rv32ivzvlsseg" -# CHECK: error: invalid arch name 'rv32ivzvlsseg', experimental extension requires explicit version number `v` +.attribute arch, "rv32iv" +# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v` diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 54e496c..3d7be42 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -36,7 +36,7 @@ ## Experimental extensions require version string to be explicitly specified .attribute arch, "rv32iv0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32izba1p0" # CHECK: attribute 5, "rv32i2p0_zba1p0" @@ -74,56 +74,56 @@ .attribute arch, "rv32ifzfh1p0" # CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0" -.attribute arch, "rv32iv0p10zvlsseg0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +.attribute arch, "rv32iv0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl32b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl64b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl128b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl256b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl512b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl1024b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl2048b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl4096b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10" .attribute arch, "rv32iv0p10zvl8192b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10" .attribute arch, "rv32iv0p10zvl16384b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10" .attribute arch, "rv32iv0p10zvl32768b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10" .attribute arch, "rv32iv0p10zvl65536b0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10" .attribute arch, "rv32i_zve32x0p10" -# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10" .attribute arch, "rv32if_zve32f0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10" .attribute arch, "rv32i_zve64x0p10" -# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32if_zve64f0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10" .attribute arch, "rv32ifd_zve64d0p10" -# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10" diff --git a/llvm/test/MC/RISCV/rvv/zvlsseg.s b/llvm/test/MC/RISCV/rvv/zvlsseg.s index 99f5e15..6845839 100644 --- a/llvm/test/MC/RISCV/rvv/zvlsseg.s +++ b/llvm/test/MC/RISCV/rvv/zvlsseg.s @@ -1,3036 +1,3034 @@ # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ -# RUN: --mattr=+experimental-zvlsseg --riscv-no-aliases \ +# RUN: --riscv-no-aliases \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \ -# RUN: --mattr=+experimental-zvlsseg %s \ -# RUN: | llvm-objdump -d --mattr=+experimental-v --mattr=+experimental-zvlsseg -M no-aliases - \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v -M no-aliases - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \ -# RUN: --mattr=+experimental-zvlsseg %s \ +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN vlseg2e8.v v8, (a0), v0.t # CHECK-INST: vlseg2e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 20 vlseg2e8.v v8, (a0) # CHECK-INST: vlseg2e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 22 vlseg2e16.v v8, (a0), v0.t # CHECK-INST: vlseg2e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 20 vlseg2e16.v v8, (a0) # CHECK-INST: vlseg2e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 22 vlseg2e32.v v8, (a0), v0.t # CHECK-INST: vlseg2e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 20 vlseg2e32.v v8, (a0) # CHECK-INST: vlseg2e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 22 vlseg2e64.v v8, (a0), v0.t # CHECK-INST: vlseg2e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 20 vlseg2e64.v v8, (a0) # CHECK-INST: vlseg2e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 22 vlseg2e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x21] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 21 vlseg2e8ff.v v8, (a0) # CHECK-INST: vlseg2e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x23] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 23 vlseg2e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x21] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 21 vlseg2e16ff.v v8, (a0) # CHECK-INST: vlseg2e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x23] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 23 vlseg2e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x21] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 21 vlseg2e32ff.v v8, (a0) # CHECK-INST: vlseg2e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x23] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 23 vlseg2e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x21] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 21 vlseg2e64ff.v v8, (a0) # CHECK-INST: vlseg2e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x23] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 23 vlsseg2e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 28 vlsseg2e8.v v8, (a0), a1 # CHECK-INST: vlsseg2e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 2a vlsseg2e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 28 vlsseg2e16.v v8, (a0), a1 # CHECK-INST: vlsseg2e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 2a vlsseg2e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 28 vlsseg2e32.v v8, (a0), a1 # CHECK-INST: vlsseg2e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 2a vlsseg2e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 28 vlsseg2e64.v v8, (a0), a1 # CHECK-INST: vlsseg2e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 2a vluxseg2ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 24 vluxseg2ei8.v v8, (a0), v4 # CHECK-INST: vluxseg2ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 26 vluxseg2ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 24 vluxseg2ei16.v v8, (a0), v4 # CHECK-INST: vluxseg2ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 26 vluxseg2ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 24 vluxseg2ei32.v v8, (a0), v4 # CHECK-INST: vluxseg2ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 26 vluxseg2ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 24 vluxseg2ei64.v v8, (a0), v4 # CHECK-INST: vluxseg2ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 26 vloxseg2ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 2c vloxseg2ei8.v v8, (a0), v4 # CHECK-INST: vloxseg2ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 2e vloxseg2ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 2c vloxseg2ei16.v v8, (a0), v4 # CHECK-INST: vloxseg2ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 2e vloxseg2ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 2c vloxseg2ei32.v v8, (a0), v4 # CHECK-INST: vloxseg2ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 2e vloxseg2ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 2c vloxseg2ei64.v v8, (a0), v4 # CHECK-INST: vloxseg2ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 2e vlseg3e8.v v8, (a0), v0.t # CHECK-INST: vlseg3e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 40 vlseg3e8.v v8, (a0) # CHECK-INST: vlseg3e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 42 vlseg3e16.v v8, (a0), v0.t # CHECK-INST: vlseg3e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 40 vlseg3e16.v v8, (a0) # CHECK-INST: vlseg3e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 42 vlseg3e32.v v8, (a0), v0.t # CHECK-INST: vlseg3e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 40 vlseg3e32.v v8, (a0) # CHECK-INST: vlseg3e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 42 vlseg3e64.v v8, (a0), v0.t # CHECK-INST: vlseg3e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 40 vlseg3e64.v v8, (a0) # CHECK-INST: vlseg3e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 42 vlseg3e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x41] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 41 vlseg3e8ff.v v8, (a0) # CHECK-INST: vlseg3e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x43] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 43 vlseg3e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x41] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 41 vlseg3e16ff.v v8, (a0) # CHECK-INST: vlseg3e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x43] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 43 vlseg3e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x41] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 41 vlseg3e32ff.v v8, (a0) # CHECK-INST: vlseg3e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x43] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 43 vlseg3e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x41] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 41 vlseg3e64ff.v v8, (a0) # CHECK-INST: vlseg3e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x43] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 43 vlsseg3e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 48 vlsseg3e8.v v8, (a0), a1 # CHECK-INST: vlsseg3e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 4a vlsseg3e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 48 vlsseg3e16.v v8, (a0), a1 # CHECK-INST: vlsseg3e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 4a vlsseg3e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 48 vlsseg3e32.v v8, (a0), a1 # CHECK-INST: vlsseg3e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 4a vlsseg3e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 48 vlsseg3e64.v v8, (a0), a1 # CHECK-INST: vlsseg3e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 4a vluxseg3ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 44 vluxseg3ei8.v v8, (a0), v4 # CHECK-INST: vluxseg3ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 46 vluxseg3ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 44 vluxseg3ei16.v v8, (a0), v4 # CHECK-INST: vluxseg3ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 46 vluxseg3ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 44 vluxseg3ei32.v v8, (a0), v4 # CHECK-INST: vluxseg3ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 46 vluxseg3ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 44 vluxseg3ei64.v v8, (a0), v4 # CHECK-INST: vluxseg3ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 46 vloxseg3ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 4c vloxseg3ei8.v v8, (a0), v4 # CHECK-INST: vloxseg3ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 4e vloxseg3ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 4c vloxseg3ei16.v v8, (a0), v4 # CHECK-INST: vloxseg3ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 4e vloxseg3ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 4c vloxseg3ei32.v v8, (a0), v4 # CHECK-INST: vloxseg3ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 4e vloxseg3ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 4c vloxseg3ei64.v v8, (a0), v4 # CHECK-INST: vloxseg3ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 4e vlseg4e8.v v8, (a0), v0.t # CHECK-INST: vlseg4e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 60 vlseg4e8.v v8, (a0) # CHECK-INST: vlseg4e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 62 vlseg4e16.v v8, (a0), v0.t # CHECK-INST: vlseg4e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 60 vlseg4e16.v v8, (a0) # CHECK-INST: vlseg4e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 62 vlseg4e32.v v8, (a0), v0.t # CHECK-INST: vlseg4e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 60 vlseg4e32.v v8, (a0) # CHECK-INST: vlseg4e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 62 vlseg4e64.v v8, (a0), v0.t # CHECK-INST: vlseg4e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 60 vlseg4e64.v v8, (a0) # CHECK-INST: vlseg4e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 62 vlseg4e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x61] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 61 vlseg4e8ff.v v8, (a0) # CHECK-INST: vlseg4e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x63] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 63 vlseg4e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x61] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 61 vlseg4e16ff.v v8, (a0) # CHECK-INST: vlseg4e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x63] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 63 vlseg4e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x61] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 61 vlseg4e32ff.v v8, (a0) # CHECK-INST: vlseg4e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x63] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 63 vlseg4e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x61] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 61 vlseg4e64ff.v v8, (a0) # CHECK-INST: vlseg4e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x63] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 63 vlsseg4e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 68 vlsseg4e8.v v8, (a0), a1 # CHECK-INST: vlsseg4e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 6a vlsseg4e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 68 vlsseg4e16.v v8, (a0), a1 # CHECK-INST: vlsseg4e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 6a vlsseg4e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 68 vlsseg4e32.v v8, (a0), a1 # CHECK-INST: vlsseg4e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 6a vlsseg4e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 68 vlsseg4e64.v v8, (a0), a1 # CHECK-INST: vlsseg4e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 6a vluxseg4ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 64 vluxseg4ei8.v v8, (a0), v4 # CHECK-INST: vluxseg4ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 66 vluxseg4ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 64 vluxseg4ei16.v v8, (a0), v4 # CHECK-INST: vluxseg4ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 66 vluxseg4ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 64 vluxseg4ei32.v v8, (a0), v4 # CHECK-INST: vluxseg4ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 66 vluxseg4ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 64 vluxseg4ei64.v v8, (a0), v4 # CHECK-INST: vluxseg4ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 66 vloxseg4ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 6c vloxseg4ei8.v v8, (a0), v4 # CHECK-INST: vloxseg4ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 6e vloxseg4ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 6c vloxseg4ei16.v v8, (a0), v4 # CHECK-INST: vloxseg4ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 6e vloxseg4ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 6c vloxseg4ei32.v v8, (a0), v4 # CHECK-INST: vloxseg4ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 6e vloxseg4ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 6c vloxseg4ei64.v v8, (a0), v4 # CHECK-INST: vloxseg4ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 6e vlseg5e8.v v8, (a0), v0.t # CHECK-INST: vlseg5e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 80 vlseg5e8.v v8, (a0) # CHECK-INST: vlseg5e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 82 vlseg5e16.v v8, (a0), v0.t # CHECK-INST: vlseg5e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 80 vlseg5e16.v v8, (a0) # CHECK-INST: vlseg5e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 82 vlseg5e32.v v8, (a0), v0.t # CHECK-INST: vlseg5e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 80 vlseg5e32.v v8, (a0) # CHECK-INST: vlseg5e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 82 vlseg5e64.v v8, (a0), v0.t # CHECK-INST: vlseg5e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 80 vlseg5e64.v v8, (a0) # CHECK-INST: vlseg5e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 82 vlseg5e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x81] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 81 vlseg5e8ff.v v8, (a0) # CHECK-INST: vlseg5e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x83] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 83 vlseg5e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x81] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 81 vlseg5e16ff.v v8, (a0) # CHECK-INST: vlseg5e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x83] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 83 vlseg5e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x81] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 81 vlseg5e32ff.v v8, (a0) # CHECK-INST: vlseg5e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x83] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 83 vlseg5e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x81] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 81 vlseg5e64ff.v v8, (a0) # CHECK-INST: vlseg5e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x83] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 83 vlsseg5e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 88 vlsseg5e8.v v8, (a0), a1 # CHECK-INST: vlsseg5e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 8a vlsseg5e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 88 vlsseg5e16.v v8, (a0), a1 # CHECK-INST: vlsseg5e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 8a vlsseg5e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 88 vlsseg5e32.v v8, (a0), a1 # CHECK-INST: vlsseg5e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 8a vlsseg5e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 88 vlsseg5e64.v v8, (a0), a1 # CHECK-INST: vlsseg5e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 8a vluxseg5ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 84 vluxseg5ei8.v v8, (a0), v4 # CHECK-INST: vluxseg5ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 86 vluxseg5ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 84 vluxseg5ei16.v v8, (a0), v4 # CHECK-INST: vluxseg5ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 86 vluxseg5ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 84 vluxseg5ei32.v v8, (a0), v4 # CHECK-INST: vluxseg5ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 86 vluxseg5ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 84 vluxseg5ei64.v v8, (a0), v4 # CHECK-INST: vluxseg5ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 86 vloxseg5ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 8c vloxseg5ei8.v v8, (a0), v4 # CHECK-INST: vloxseg5ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 8e vloxseg5ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 8c vloxseg5ei16.v v8, (a0), v4 # CHECK-INST: vloxseg5ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 8e vloxseg5ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 8c vloxseg5ei32.v v8, (a0), v4 # CHECK-INST: vloxseg5ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 8e vloxseg5ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 8c vloxseg5ei64.v v8, (a0), v4 # CHECK-INST: vloxseg5ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 8e vlseg6e8.v v8, (a0), v0.t # CHECK-INST: vlseg6e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 a0 vlseg6e8.v v8, (a0) # CHECK-INST: vlseg6e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 a2 vlseg6e16.v v8, (a0), v0.t # CHECK-INST: vlseg6e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 a0 vlseg6e16.v v8, (a0) # CHECK-INST: vlseg6e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 a2 vlseg6e32.v v8, (a0), v0.t # CHECK-INST: vlseg6e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 a0 vlseg6e32.v v8, (a0) # CHECK-INST: vlseg6e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 a2 vlseg6e64.v v8, (a0), v0.t # CHECK-INST: vlseg6e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 a0 vlseg6e64.v v8, (a0) # CHECK-INST: vlseg6e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 a2 vlseg6e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xa1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 a1 vlseg6e8ff.v v8, (a0) # CHECK-INST: vlseg6e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xa3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 a3 vlseg6e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xa1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 a1 vlseg6e16ff.v v8, (a0) # CHECK-INST: vlseg6e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xa3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 a3 vlseg6e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xa1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 a1 vlseg6e32ff.v v8, (a0) # CHECK-INST: vlseg6e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xa3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 a3 vlseg6e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xa1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 a1 vlseg6e64ff.v v8, (a0) # CHECK-INST: vlseg6e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xa3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 a3 vlsseg6e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 a8 vlsseg6e8.v v8, (a0), a1 # CHECK-INST: vlsseg6e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 aa vlsseg6e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 a8 vlsseg6e16.v v8, (a0), a1 # CHECK-INST: vlsseg6e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 aa vlsseg6e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 a8 vlsseg6e32.v v8, (a0), a1 # CHECK-INST: vlsseg6e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 aa vlsseg6e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 a8 vlsseg6e64.v v8, (a0), a1 # CHECK-INST: vlsseg6e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 aa vluxseg6ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 a4 vluxseg6ei8.v v8, (a0), v4 # CHECK-INST: vluxseg6ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 a6 vluxseg6ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 a4 vluxseg6ei16.v v8, (a0), v4 # CHECK-INST: vluxseg6ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 a6 vluxseg6ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 a4 vluxseg6ei32.v v8, (a0), v4 # CHECK-INST: vluxseg6ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 a6 vluxseg6ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 a4 vluxseg6ei64.v v8, (a0), v4 # CHECK-INST: vluxseg6ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 a6 vloxseg6ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 ac vloxseg6ei8.v v8, (a0), v4 # CHECK-INST: vloxseg6ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 ae vloxseg6ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 ac vloxseg6ei16.v v8, (a0), v4 # CHECK-INST: vloxseg6ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 ae vloxseg6ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 ac vloxseg6ei32.v v8, (a0), v4 # CHECK-INST: vloxseg6ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 ae vloxseg6ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 ac vloxseg6ei64.v v8, (a0), v4 # CHECK-INST: vloxseg6ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 ae vlseg7e8.v v8, (a0), v0.t # CHECK-INST: vlseg7e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 c0 vlseg7e8.v v8, (a0) # CHECK-INST: vlseg7e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 c2 vlseg7e16.v v8, (a0), v0.t # CHECK-INST: vlseg7e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 c0 vlseg7e16.v v8, (a0) # CHECK-INST: vlseg7e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 c2 vlseg7e32.v v8, (a0), v0.t # CHECK-INST: vlseg7e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 c0 vlseg7e32.v v8, (a0) # CHECK-INST: vlseg7e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 c2 vlseg7e64.v v8, (a0), v0.t # CHECK-INST: vlseg7e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 c0 vlseg7e64.v v8, (a0) # CHECK-INST: vlseg7e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 c2 vlseg7e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xc1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 c1 vlseg7e8ff.v v8, (a0) # CHECK-INST: vlseg7e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xc3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 c3 vlseg7e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xc1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 c1 vlseg7e16ff.v v8, (a0) # CHECK-INST: vlseg7e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xc3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 c3 vlseg7e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xc1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 c1 vlseg7e32ff.v v8, (a0) # CHECK-INST: vlseg7e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xc3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 c3 vlseg7e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xc1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 c1 vlseg7e64ff.v v8, (a0) # CHECK-INST: vlseg7e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xc3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 c3 vlsseg7e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 c8 vlsseg7e8.v v8, (a0), a1 # CHECK-INST: vlsseg7e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 ca vlsseg7e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 c8 vlsseg7e16.v v8, (a0), a1 # CHECK-INST: vlsseg7e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 ca vlsseg7e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 c8 vlsseg7e32.v v8, (a0), a1 # CHECK-INST: vlsseg7e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 ca vlsseg7e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 c8 vlsseg7e64.v v8, (a0), a1 # CHECK-INST: vlsseg7e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 ca vluxseg7ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 c4 vluxseg7ei8.v v8, (a0), v4 # CHECK-INST: vluxseg7ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 c6 vluxseg7ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 c4 vluxseg7ei16.v v8, (a0), v4 # CHECK-INST: vluxseg7ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 c6 vluxseg7ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 c4 vluxseg7ei32.v v8, (a0), v4 # CHECK-INST: vluxseg7ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 c6 vluxseg7ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 c4 vluxseg7ei64.v v8, (a0), v4 # CHECK-INST: vluxseg7ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 c6 vloxseg7ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 cc vloxseg7ei8.v v8, (a0), v4 # CHECK-INST: vloxseg7ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 ce vloxseg7ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 cc vloxseg7ei16.v v8, (a0), v4 # CHECK-INST: vloxseg7ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 ce vloxseg7ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 cc vloxseg7ei32.v v8, (a0), v4 # CHECK-INST: vloxseg7ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 ce vloxseg7ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 cc vloxseg7ei64.v v8, (a0), v4 # CHECK-INST: vloxseg7ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 ce vlseg8e8.v v8, (a0), v0.t # CHECK-INST: vlseg8e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 e0 vlseg8e8.v v8, (a0) # CHECK-INST: vlseg8e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 e2 vlseg8e16.v v8, (a0), v0.t # CHECK-INST: vlseg8e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 e0 vlseg8e16.v v8, (a0) # CHECK-INST: vlseg8e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 e2 vlseg8e32.v v8, (a0), v0.t # CHECK-INST: vlseg8e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 e0 vlseg8e32.v v8, (a0) # CHECK-INST: vlseg8e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 e2 vlseg8e64.v v8, (a0), v0.t # CHECK-INST: vlseg8e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 e0 vlseg8e64.v v8, (a0) # CHECK-INST: vlseg8e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 e2 vlseg8e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xe1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 e1 vlseg8e8ff.v v8, (a0) # CHECK-INST: vlseg8e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xe3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 05 e3 vlseg8e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xe1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 e1 vlseg8e16ff.v v8, (a0) # CHECK-INST: vlseg8e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xe3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 05 e3 vlseg8e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xe1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 e1 vlseg8e32ff.v v8, (a0) # CHECK-INST: vlseg8e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xe3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 05 e3 vlseg8e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xe1] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 e1 vlseg8e64ff.v v8, (a0) # CHECK-INST: vlseg8e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xe3] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 05 e3 vlsseg8e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 e8 vlsseg8e8.v v8, (a0), a1 # CHECK-INST: vlsseg8e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 b5 ea vlsseg8e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 e8 vlsseg8e16.v v8, (a0), a1 # CHECK-INST: vlsseg8e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 b5 ea vlsseg8e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 e8 vlsseg8e32.v v8, (a0), a1 # CHECK-INST: vlsseg8e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 b5 ea vlsseg8e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 e8 vlsseg8e64.v v8, (a0), a1 # CHECK-INST: vlsseg8e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 b5 ea vluxseg8ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 e4 vluxseg8ei8.v v8, (a0), v4 # CHECK-INST: vluxseg8ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 e6 vluxseg8ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 e4 vluxseg8ei16.v v8, (a0), v4 # CHECK-INST: vluxseg8ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 e6 vluxseg8ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 e4 vluxseg8ei32.v v8, (a0), v4 # CHECK-INST: vluxseg8ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 e6 vluxseg8ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 e4 vluxseg8ei64.v v8, (a0), v4 # CHECK-INST: vluxseg8ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 e6 vloxseg8ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 ec vloxseg8ei8.v v8, (a0), v4 # CHECK-INST: vloxseg8ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 04 45 ee vloxseg8ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 ec vloxseg8ei16.v v8, (a0), v4 # CHECK-INST: vloxseg8ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 54 45 ee vloxseg8ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 ec vloxseg8ei32.v v8, (a0), v4 # CHECK-INST: vloxseg8ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 64 45 ee vloxseg8ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 ec vloxseg8ei64.v v8, (a0), v4 # CHECK-INST: vloxseg8ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 07 74 45 ee vsseg2e8.v v24, (a0), v0.t # CHECK-INST: vsseg2e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 20 vsseg2e8.v v24, (a0) # CHECK-INST: vsseg2e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 22 vsseg2e16.v v24, (a0), v0.t # CHECK-INST: vsseg2e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 20 vsseg2e16.v v24, (a0) # CHECK-INST: vsseg2e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 22 vsseg2e32.v v24, (a0), v0.t # CHECK-INST: vsseg2e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 20 vsseg2e32.v v24, (a0) # CHECK-INST: vsseg2e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 22 vsseg2e64.v v24, (a0), v0.t # CHECK-INST: vsseg2e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x20] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 20 vsseg2e64.v v24, (a0) # CHECK-INST: vsseg2e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x22] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 22 vssseg2e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 28 vssseg2e8.v v24, (a0), a1 # CHECK-INST: vssseg2e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 2a vssseg2e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 28 vssseg2e16.v v24, (a0), a1 # CHECK-INST: vssseg2e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 2a vssseg2e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 28 vssseg2e32.v v24, (a0), a1 # CHECK-INST: vssseg2e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 2a vssseg2e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x28] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 28 vssseg2e64.v v24, (a0), a1 # CHECK-INST: vssseg2e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 2a vsuxseg2ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 24 vsuxseg2ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 26 vsuxseg2ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 24 vsuxseg2ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 26 vsuxseg2ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 24 vsuxseg2ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 26 vsuxseg2ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 24 vsuxseg2ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 26 vsoxseg2ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 2c vsoxseg2ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 2e vsoxseg2ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 2c vsoxseg2ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 2e vsoxseg2ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 2c vsoxseg2ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 2e vsoxseg2ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 2c vsoxseg2ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 2e vsseg3e8.v v24, (a0), v0.t # CHECK-INST: vsseg3e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 40 vsseg3e8.v v24, (a0) # CHECK-INST: vsseg3e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 42 vsseg3e16.v v24, (a0), v0.t # CHECK-INST: vsseg3e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 40 vsseg3e16.v v24, (a0) # CHECK-INST: vsseg3e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 42 vsseg3e32.v v24, (a0), v0.t # CHECK-INST: vsseg3e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 40 vsseg3e32.v v24, (a0) # CHECK-INST: vsseg3e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 42 vsseg3e64.v v24, (a0), v0.t # CHECK-INST: vsseg3e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x40] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 40 vsseg3e64.v v24, (a0) # CHECK-INST: vsseg3e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 42 vssseg3e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 48 vssseg3e8.v v24, (a0), a1 # CHECK-INST: vssseg3e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 4a vssseg3e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 48 vssseg3e16.v v24, (a0), a1 # CHECK-INST: vssseg3e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 4a vssseg3e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 48 vssseg3e32.v v24, (a0), a1 # CHECK-INST: vssseg3e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 4a vssseg3e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 48 vssseg3e64.v v24, (a0), a1 # CHECK-INST: vssseg3e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 4a vsuxseg3ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 44 vsuxseg3ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 46 vsuxseg3ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 44 vsuxseg3ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 46 vsuxseg3ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 44 vsuxseg3ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 46 vsuxseg3ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 44 vsuxseg3ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 46 vsoxseg3ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 4c vsoxseg3ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 4e vsoxseg3ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 4c vsoxseg3ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 4e vsoxseg3ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 4c vsoxseg3ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 4e vsoxseg3ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 4c vsoxseg3ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 4e vsseg4e8.v v24, (a0), v0.t # CHECK-INST: vsseg4e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 60 vsseg4e8.v v24, (a0) # CHECK-INST: vsseg4e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 62 vsseg4e16.v v24, (a0), v0.t # CHECK-INST: vsseg4e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 60 vsseg4e16.v v24, (a0) # CHECK-INST: vsseg4e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 62 vsseg4e32.v v24, (a0), v0.t # CHECK-INST: vsseg4e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 60 vsseg4e32.v v24, (a0) # CHECK-INST: vsseg4e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 62 vsseg4e64.v v24, (a0), v0.t # CHECK-INST: vsseg4e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x60] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 60 vsseg4e64.v v24, (a0) # CHECK-INST: vsseg4e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x62] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 62 vssseg4e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 68 vssseg4e8.v v24, (a0), a1 # CHECK-INST: vssseg4e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 6a vssseg4e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 68 vssseg4e16.v v24, (a0), a1 # CHECK-INST: vssseg4e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 6a vssseg4e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 68 vssseg4e32.v v24, (a0), a1 # CHECK-INST: vssseg4e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 6a vssseg4e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x68] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 68 vssseg4e64.v v24, (a0), a1 # CHECK-INST: vssseg4e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 6a vsuxseg4ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 64 vsuxseg4ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 66 vsuxseg4ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 64 vsuxseg4ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 66 vsuxseg4ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 64 vsuxseg4ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 66 vsuxseg4ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 64 vsuxseg4ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 66 vsoxseg4ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 6c vsoxseg4ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 6e vsoxseg4ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 6c vsoxseg4ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 6e vsoxseg4ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 6c vsoxseg4ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 6e vsoxseg4ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 6c vsoxseg4ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 6e vsseg5e8.v v24, (a0), v0.t # CHECK-INST: vsseg5e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 80 vsseg5e8.v v24, (a0) # CHECK-INST: vsseg5e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 82 vsseg5e16.v v24, (a0), v0.t # CHECK-INST: vsseg5e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 80 vsseg5e16.v v24, (a0) # CHECK-INST: vsseg5e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 82 vsseg5e32.v v24, (a0), v0.t # CHECK-INST: vsseg5e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 80 vsseg5e32.v v24, (a0) # CHECK-INST: vsseg5e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 82 vsseg5e64.v v24, (a0), v0.t # CHECK-INST: vsseg5e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x80] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 80 vsseg5e64.v v24, (a0) # CHECK-INST: vsseg5e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 82 vssseg5e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 88 vssseg5e8.v v24, (a0), a1 # CHECK-INST: vssseg5e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 8a vssseg5e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 88 vssseg5e16.v v24, (a0), a1 # CHECK-INST: vssseg5e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 8a vssseg5e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 88 vssseg5e32.v v24, (a0), a1 # CHECK-INST: vssseg5e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 8a vssseg5e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x88] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 88 vssseg5e64.v v24, (a0), a1 # CHECK-INST: vssseg5e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 8a vsuxseg5ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 84 vsuxseg5ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 86 vsuxseg5ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 84 vsuxseg5ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 86 vsuxseg5ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 84 vsuxseg5ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 86 vsuxseg5ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 84 vsuxseg5ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 86 vsoxseg5ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 8c vsoxseg5ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 8e vsoxseg5ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 8c vsoxseg5ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 8e vsoxseg5ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 8c vsoxseg5ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 8e vsoxseg5ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 8c vsoxseg5ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 8e vsseg6e8.v v24, (a0), v0.t # CHECK-INST: vsseg6e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 a0 vsseg6e8.v v24, (a0) # CHECK-INST: vsseg6e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 a2 vsseg6e16.v v24, (a0), v0.t # CHECK-INST: vsseg6e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 a0 vsseg6e16.v v24, (a0) # CHECK-INST: vsseg6e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 a2 vsseg6e32.v v24, (a0), v0.t # CHECK-INST: vsseg6e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 a0 vsseg6e32.v v24, (a0) # CHECK-INST: vsseg6e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 a2 vsseg6e64.v v24, (a0), v0.t # CHECK-INST: vsseg6e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0xa0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 a0 vsseg6e64.v v24, (a0) # CHECK-INST: vsseg6e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 a2 vssseg6e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 a8 vssseg6e8.v v24, (a0), a1 # CHECK-INST: vssseg6e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 aa vssseg6e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 a8 vssseg6e16.v v24, (a0), a1 # CHECK-INST: vssseg6e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 aa vssseg6e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 a8 vssseg6e32.v v24, (a0), a1 # CHECK-INST: vssseg6e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 aa vssseg6e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 a8 vssseg6e64.v v24, (a0), a1 # CHECK-INST: vssseg6e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 aa vsuxseg6ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 a4 vsuxseg6ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 a6 vsuxseg6ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 a4 vsuxseg6ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 a6 vsuxseg6ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 a4 vsuxseg6ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 a6 vsuxseg6ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 a4 vsuxseg6ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 a6 vsoxseg6ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 ac vsoxseg6ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 ae vsoxseg6ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 ac vsoxseg6ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 ae vsoxseg6ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 ac vsoxseg6ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 ae vsoxseg6ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 ac vsoxseg6ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 ae vsseg7e8.v v24, (a0), v0.t # CHECK-INST: vsseg7e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 c0 vsseg7e8.v v24, (a0) # CHECK-INST: vsseg7e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 c2 vsseg7e16.v v24, (a0), v0.t # CHECK-INST: vsseg7e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 c0 vsseg7e16.v v24, (a0) # CHECK-INST: vsseg7e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 c2 vsseg7e32.v v24, (a0), v0.t # CHECK-INST: vsseg7e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 c0 vsseg7e32.v v24, (a0) # CHECK-INST: vsseg7e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 c2 vsseg7e64.v v24, (a0), v0.t # CHECK-INST: vsseg7e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0xc0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 c0 vsseg7e64.v v24, (a0) # CHECK-INST: vsseg7e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0xc2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 c2 vssseg7e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 c8 vssseg7e8.v v24, (a0), a1 # CHECK-INST: vssseg7e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 ca vssseg7e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 c8 vssseg7e16.v v24, (a0), a1 # CHECK-INST: vssseg7e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 ca vssseg7e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 c8 vssseg7e32.v v24, (a0), a1 # CHECK-INST: vssseg7e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 ca vssseg7e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 c8 vssseg7e64.v v24, (a0), a1 # CHECK-INST: vssseg7e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xca] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 ca vsuxseg7ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 c4 vsuxseg7ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 c6 vsuxseg7ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 c4 vsuxseg7ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 c6 vsuxseg7ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 c4 vsuxseg7ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 c6 vsuxseg7ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 c4 vsuxseg7ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 c6 vsoxseg7ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 cc vsoxseg7ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 ce vsoxseg7ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 cc vsoxseg7ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 ce vsoxseg7ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 cc vsoxseg7ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 ce vsoxseg7ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 cc vsoxseg7ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 ce vsseg8e8.v v24, (a0), v0.t # CHECK-INST: vsseg8e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 e0 vsseg8e8.v v24, (a0) # CHECK-INST: vsseg8e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 05 e2 vsseg8e16.v v24, (a0), v0.t # CHECK-INST: vsseg8e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 e0 vsseg8e16.v v24, (a0) # CHECK-INST: vsseg8e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 05 e2 vsseg8e32.v v24, (a0), v0.t # CHECK-INST: vsseg8e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 e0 vsseg8e32.v v24, (a0) # CHECK-INST: vsseg8e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 05 e2 vsseg8e64.v v24, (a0), v0.t # CHECK-INST: vsseg8e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0xe0] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 e0 vsseg8e64.v v24, (a0) # CHECK-INST: vsseg8e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0xe2] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 05 e2 vssseg8e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 e8 vssseg8e8.v v24, (a0), a1 # CHECK-INST: vssseg8e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c b5 ea vssseg8e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 e8 vssseg8e16.v v24, (a0), a1 # CHECK-INST: vssseg8e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c b5 ea vssseg8e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 e8 vssseg8e32.v v24, (a0), a1 # CHECK-INST: vssseg8e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c b5 ea vssseg8e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 e8 vssseg8e64.v v24, (a0), a1 # CHECK-INST: vssseg8e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xea] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c b5 ea vsuxseg8ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 e4 vsuxseg8ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 e6 vsuxseg8ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 e4 vsuxseg8ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 e6 vsuxseg8ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 e4 vsuxseg8ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 e6 vsuxseg8ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 e4 vsuxseg8ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xe6] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 e6 vsoxseg8ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 ec vsoxseg8ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 0c 45 ee vsoxseg8ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 ec vsoxseg8ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 5c 45 ee vsoxseg8ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 ec vsoxseg8ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 6c 45 ee vsoxseg8ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 ec vsoxseg8ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvlsseg' +# CHECK-ERROR: instruction requires the following: 'V' # CHECK-UNKNOWN: 27 7c 45 ee -- 2.7.4