From 7a08381403b54cd8998f3c922f18b65867e3c07c Mon Sep 17 00:00:00 2001 From: Richard Trieu Date: Thu, 18 Feb 2016 22:09:30 +0000 Subject: [PATCH] Remove uses of builtin comma operator. Cleanup for upcoming Clang warning -Wcomma. No functionality change intended. llvm-svn: 261270 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 3 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 6 +- llvm/lib/Analysis/ValueTracking.cpp | 9 ++- llvm/lib/CodeGen/CalcSpillWeights.cpp | 12 ++-- llvm/lib/CodeGen/LiveDebugVariables.cpp | 18 ++++-- llvm/lib/CodeGen/LiveInterval.cpp | 8 ++- llvm/lib/CodeGen/MachineInstr.cpp | 6 +- llvm/lib/CodeGen/MachineModuleInfo.cpp | 3 +- llvm/lib/CodeGen/MachineSink.cpp | 6 +- llvm/lib/CodeGen/MachineTraceMetrics.cpp | 12 ++-- llvm/lib/CodeGen/RegAllocGreedy.cpp | 32 +++++++---- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 44 +++++++++------ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 +- llvm/lib/IR/Function.cpp | 14 +++-- llvm/lib/MC/MCParser/AsmLexer.cpp | 65 ++++++++++++++-------- llvm/lib/Support/APFloat.cpp | 4 +- llvm/lib/Support/APInt.cpp | 6 +- llvm/lib/Support/FileUtilities.cpp | 6 +- llvm/lib/Support/IntEqClasses.cpp | 13 +++-- llvm/lib/Support/Unix/Process.inc | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 36 ++++++++---- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 40 +++++++------ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 12 ++-- llvm/lib/Target/X86/X86FloatingPoint.cpp | 3 +- llvm/lib/Transforms/IPO/MergeFunctions.cpp | 3 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 17 ++++-- .../Transforms/InstCombine/InstCombineCalls.cpp | 6 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 29 +++++++--- .../InstCombine/InstCombineMulDivRem.cpp | 11 ++-- llvm/lib/Transforms/Scalar/Sink.cpp | 6 +- llvm/lib/Transforms/Utils/CloneFunction.cpp | 3 +- .../Transforms/Utils/PromoteMemoryToRegister.cpp | 3 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 40 +++++++------ llvm/tools/llvm-diff/DifferenceEngine.cpp | 10 +++- llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp | 22 ++++---- 35 files changed, 329 insertions(+), 187 deletions(-) diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp index 2d92da1..74aae76 100644 --- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp +++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp @@ -1554,7 +1554,8 @@ bool BasicAAResult::constantOffsetHeuristic( unsigned V0ZExtBits = 0, V0SExtBits = 0, V1ZExtBits = 0, V1SExtBits = 0; const Value *V0 = GetLinearExpression(Var0.V, V0Scale, V0Offset, V0ZExtBits, V0SExtBits, DL, 0, AC, DT, NSW, NUW); - NSW = true, NUW = true; + NSW = true; + NUW = true; const Value *V1 = GetLinearExpression(Var1.V, V1Scale, V1Offset, V1ZExtBits, V1SExtBits, DL, 0, AC, DT, NSW, NUW); diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index f371feb..7227d48 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -1325,8 +1325,10 @@ bool MemoryDepChecker::areDepsSafe(DepCandidates &AccessSets, AccessSets.findValue(AccessSets.getLeaderValue(CurAccess)); // Check accesses within this set. - EquivalenceClasses::member_iterator AI, AE; - AI = AccessSets.member_begin(I), AE = AccessSets.member_end(); + EquivalenceClasses::member_iterator AI = + AccessSets.member_begin(I); + EquivalenceClasses::member_iterator AE = + AccessSets.member_end(); // Check every access pair. while (AI != AE) { diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 6dff45f..fafbcef 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -1024,7 +1024,8 @@ static void computeKnownBitsFromShiftOperator(Operator *I, // It would be more-clearly correct to use the two temporaries for this // calculation. Reusing the APInts here to prevent unnecessary allocations. - KnownZero.clearAllBits(), KnownOne.clearAllBits(); + KnownZero.clearAllBits(); + KnownOne.clearAllBits(); // If we know the shifter operand is nonzero, we can sometimes infer more // known bits. However this is expensive to compute, so be lazy about it and @@ -1069,8 +1070,10 @@ static void computeKnownBitsFromShiftOperator(Operator *I, // return anything we'd like, but we need to make sure the sets of known bits // stay disjoint (it should be better for some other code to actually // propagate the undef than to pick a value here using known bits). - if ((KnownZero & KnownOne) != 0) - KnownZero.clearAllBits(), KnownOne.clearAllBits(); + if ((KnownZero & KnownOne) != 0) { + KnownZero.clearAllBits(); + KnownOne.clearAllBits(); + } } static void computeKnownBitsFromOperator(Operator *I, APInt &KnownZero, diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp index 26aa46f..4877f00 100644 --- a/llvm/lib/CodeGen/CalcSpillWeights.cpp +++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp @@ -192,11 +192,15 @@ VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) { // FIXME: we probably shouldn't use floats at all. volatile float hweight = Hint[hint] += weight; if (TargetRegisterInfo::isPhysicalRegister(hint)) { - if (hweight > bestPhys && mri.isAllocatable(hint)) - bestPhys = hweight, hintPhys = hint; + if (hweight > bestPhys && mri.isAllocatable(hint)) { + bestPhys = hweight; + hintPhys = hint; + } } else { - if (hweight > bestVirt) - bestVirt = hweight, hintVirt = hint; + if (hweight > bestVirt) { + bestVirt = hweight; + hintVirt = hint; + } } } diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp index e49f8bf..0ca267c 100644 --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -172,8 +172,10 @@ public: return L1; // Splice L2 before L1's members. UserValue *End = L2; - while (End->next) - End->leader = L1, End = End->next; + while (End->next) { + End->leader = L1; + End = End->next; + } End->leader = L1; End->next = L1->next; L1->next = L2; @@ -554,8 +556,10 @@ void UserValue::extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, Kills->push_back(Start); return; } - if (Segment->end < Stop) - Stop = Segment->end, ToEnd = false; + if (Segment->end < Stop) { + Stop = Segment->end; + ToEnd = false; + } } // There could already be a short def at Start. @@ -569,8 +573,10 @@ void UserValue::extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, } // Limited by the next def. - if (I.valid() && I.start() < Stop) - Stop = I.start(), ToEnd = false; + if (I.valid() && I.start() < Stop) { + Stop = I.start(); + ToEnd = false; + } // Limited by VNI's live range. else if (!ToEnd && Kills) Kills->push_back(Stop); diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp index d80acc0..e639320 100644 --- a/llvm/lib/CodeGen/LiveInterval.cpp +++ b/llvm/lib/CodeGen/LiveInterval.cpp @@ -309,10 +309,12 @@ LiveRange::iterator LiveRange::find(SlotIndex Pos) { size_t Len = size(); do { size_t Mid = Len >> 1; - if (Pos < I[Mid].end) + if (Pos < I[Mid].end) { Len = Mid; - else - I += Mid + 1, Len -= Mid + 1; + } else { + I += Mid + 1; + Len -= Mid + 1; + } } while (Len); return I; } diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 805acb9..4103253 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1234,8 +1234,10 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect( unsigned MachineInstr::getBundleSize() const { MachineBasicBlock::const_instr_iterator I = getIterator(); unsigned Size = 0; - while (I->isBundledWithSucc()) - ++Size, ++I; + while (I->isBundledWithSucc()) { + ++Size; + ++I; + } return Size; } diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp index 1956a70..244e3fb 100644 --- a/llvm/lib/CodeGen/MachineModuleInfo.cpp +++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp @@ -396,7 +396,8 @@ void MachineModuleInfo::TidyLandingPads(DenseMap *LPMap) { LandingPad.BeginLabels.erase(LandingPad.BeginLabels.begin() + j); LandingPad.EndLabels.erase(LandingPad.EndLabels.begin() + j); - --j, --e; + --j; + --e; } // Remove landing pads with no try-ranges. diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index a10bd7f..b1f3875 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -344,8 +344,10 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) { continue; } - if (SinkInstruction(MI, SawStore, AllSuccessors)) - ++NumSunk, MadeChange = true; + if (SinkInstruction(MI, SawStore, AllSuccessors)) { + ++NumSunk; + MadeChange = true; + } // If we just processed the first instruction in the block, we're done. } while (!ProcessedBegin); diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index f7edacd..3814459 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -328,8 +328,10 @@ MinInstrCountEnsemble::pickTracePred(const MachineBasicBlock *MBB) { continue; // Pick the predecessor that would give this block the smallest InstrDepth. unsigned Depth = PredTBI->InstrDepth + CurCount; - if (!Best || Depth < BestDepth) - Best = Pred, BestDepth = Depth; + if (!Best || Depth < BestDepth) { + Best = Pred; + BestDepth = Depth; + } } return Best; } @@ -356,8 +358,10 @@ MinInstrCountEnsemble::pickTraceSucc(const MachineBasicBlock *MBB) { continue; // Pick the successor that would give this block the smallest InstrHeight. unsigned Height = SuccTBI->InstrHeight; - if (!Best || Height < BestHeight) - Best = Succ, BestHeight = Height; + if (!Best || Height < BestHeight) { + Best = Succ; + BestHeight = Height; + } } return Best; } diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 945cb9e..b243d43 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -954,22 +954,28 @@ bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf, // Interference for the live-in value. if (BI.LiveIn) { - if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) - BC.Entry = SpillPlacement::MustSpill, ++Ins; - else if (Intf.first() < BI.FirstInstr) - BC.Entry = SpillPlacement::PrefSpill, ++Ins; - else if (Intf.first() < BI.LastInstr) + if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) { + BC.Entry = SpillPlacement::MustSpill; ++Ins; + } else if (Intf.first() < BI.FirstInstr) { + BC.Entry = SpillPlacement::PrefSpill; + ++Ins; + } else if (Intf.first() < BI.LastInstr) { + ++Ins; + } } // Interference for the live-out value. if (BI.LiveOut) { - if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) - BC.Exit = SpillPlacement::MustSpill, ++Ins; - else if (Intf.last() > BI.LastInstr) - BC.Exit = SpillPlacement::PrefSpill, ++Ins; - else if (Intf.last() > BI.FirstInstr) + if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) { + BC.Exit = SpillPlacement::MustSpill; + ++Ins; + } else if (Intf.last() > BI.LastInstr) { + BC.Exit = SpillPlacement::PrefSpill; ++Ins; + } else if (Intf.last() > BI.FirstInstr) { + ++Ins; + } } // Accumulate the total frequency of inserted spill code. @@ -1392,8 +1398,10 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, if (i == BestCand || !GlobalCand[i].PhysReg) continue; unsigned Count = GlobalCand[i].LiveBundles.count(); - if (Count < WorstCount) - Worst = i, WorstCount = Count; + if (Count < WorstCount) { + Worst = i; + WorstCount = Count; + } } --NumCands; GlobalCand[Worst] = GlobalCand[NumCands]; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 73e6c46..79d307a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -677,25 +677,33 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, // now, just use the tightest assertzext/assertsext possible. bool isSExt = true; EVT FromVT(MVT::Other); - if (NumSignBits == RegSize) - isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 - else if (NumZeroBits >= RegSize-1) - isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 - else if (NumSignBits > RegSize-8) - isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 - else if (NumZeroBits >= RegSize-8) - isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 - else if (NumSignBits > RegSize-16) - isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 - else if (NumZeroBits >= RegSize-16) - isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 - else if (NumSignBits > RegSize-32) - isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 - else if (NumZeroBits >= RegSize-32) - isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 - else + if (NumSignBits == RegSize) { + isSExt = true; // ASSERT SEXT 1 + FromVT = MVT::i1; + } else if (NumZeroBits >= RegSize - 1) { + isSExt = false; // ASSERT ZEXT 1 + FromVT = MVT::i1; + } else if (NumSignBits > RegSize - 8) { + isSExt = true; // ASSERT SEXT 8 + FromVT = MVT::i8; + } else if (NumZeroBits >= RegSize - 8) { + isSExt = false; // ASSERT ZEXT 8 + FromVT = MVT::i8; + } else if (NumSignBits > RegSize - 16) { + isSExt = true; // ASSERT SEXT 16 + FromVT = MVT::i16; + } else if (NumZeroBits >= RegSize - 16) { + isSExt = false; // ASSERT ZEXT 16 + FromVT = MVT::i16; + } else if (NumSignBits > RegSize - 32) { + isSExt = true; // ASSERT SEXT 32 + FromVT = MVT::i32; + } else if (NumZeroBits >= RegSize - 32) { + isSExt = false; // ASSERT ZEXT 32 + FromVT = MVT::i32; + } else { continue; - + } // Add an assertion node. assert(FromVT != MVT::Other); Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 39a13c8..3881415 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2268,8 +2268,10 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, C = dyn_cast(Op.getOperand(0)); GA = dyn_cast(Op.getOperand(1)); } - if (!C || !GA) - C = nullptr, GA = nullptr; + if (!C || !GA) { + C = nullptr; + GA = nullptr; + } } // If we find a valid operand, map to the TargetXXX version so that the diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp index da1dded..a0eec5f 100644 --- a/llvm/lib/IR/Function.cpp +++ b/llvm/lib/IR/Function.cpp @@ -882,11 +882,17 @@ bool Function::hasAddressTaken(const User* *PutOffender) const { const User *FU = U.getUser(); if (isa(FU)) continue; - if (!isa(FU) && !isa(FU)) - return PutOffender ? (*PutOffender = FU, true) : true; + if (!isa(FU) && !isa(FU)) { + if (PutOffender) + *PutOffender = FU; + return true; + } ImmutableCallSite CS(cast(FU)); - if (!CS.isCallee(&U)) - return PutOffender ? (*PutOffender = FU, true) : true; + if (!CS.isCallee(&U)) { + if (PutOffender) + *PutOffender = FU; + return true; + } } return false; } diff --git a/llvm/lib/MC/MCParser/AsmLexer.cpp b/llvm/lib/MC/MCParser/AsmLexer.cpp index 36c1920..424c8ae 100644 --- a/llvm/lib/MC/MCParser/AsmLexer.cpp +++ b/llvm/lib/MC/MCParser/AsmLexer.cpp @@ -168,9 +168,13 @@ AsmToken AsmLexer::LexIdentifier() { /// C-Style Comment: /* ... */ AsmToken AsmLexer::LexSlash() { switch (*CurPtr) { - case '*': break; // C style comment. - case '/': return ++CurPtr, LexLineComment(); - default: return AsmToken(AsmToken::Slash, StringRef(CurPtr-1, 1)); + case '*': + break; // C style comment. + case '/': + ++CurPtr; + return LexLineComment(); + default: + return AsmToken(AsmToken::Slash, StringRef(CurPtr - 1, 1)); } // C Style comment. @@ -557,21 +561,29 @@ AsmToken AsmLexer::LexToken() { case '@': return AsmToken(AsmToken::At, StringRef(TokStart, 1)); case '\\': return AsmToken(AsmToken::BackSlash, StringRef(TokStart, 1)); case '=': - if (*CurPtr == '=') - return ++CurPtr, AsmToken(AsmToken::EqualEqual, StringRef(TokStart, 2)); + if (*CurPtr == '=') { + ++CurPtr; + return AsmToken(AsmToken::EqualEqual, StringRef(TokStart, 2)); + } return AsmToken(AsmToken::Equal, StringRef(TokStart, 1)); case '|': - if (*CurPtr == '|') - return ++CurPtr, AsmToken(AsmToken::PipePipe, StringRef(TokStart, 2)); + if (*CurPtr == '|') { + ++CurPtr; + return AsmToken(AsmToken::PipePipe, StringRef(TokStart, 2)); + } return AsmToken(AsmToken::Pipe, StringRef(TokStart, 1)); case '^': return AsmToken(AsmToken::Caret, StringRef(TokStart, 1)); case '&': - if (*CurPtr == '&') - return ++CurPtr, AsmToken(AsmToken::AmpAmp, StringRef(TokStart, 2)); + if (*CurPtr == '&') { + ++CurPtr; + return AsmToken(AsmToken::AmpAmp, StringRef(TokStart, 2)); + } return AsmToken(AsmToken::Amp, StringRef(TokStart, 1)); case '!': - if (*CurPtr == '=') - return ++CurPtr, AsmToken(AsmToken::ExclaimEqual, StringRef(TokStart, 2)); + if (*CurPtr == '=') { + ++CurPtr; + return AsmToken(AsmToken::ExclaimEqual, StringRef(TokStart, 2)); + } return AsmToken(AsmToken::Exclaim, StringRef(TokStart, 1)); case '%': return AsmToken(AsmToken::Percent, StringRef(TokStart, 1)); case '/': return LexSlash(); @@ -583,21 +595,28 @@ AsmToken AsmLexer::LexToken() { return LexDigit(); case '<': switch (*CurPtr) { - case '<': return ++CurPtr, AsmToken(AsmToken::LessLess, - StringRef(TokStart, 2)); - case '=': return ++CurPtr, AsmToken(AsmToken::LessEqual, - StringRef(TokStart, 2)); - case '>': return ++CurPtr, AsmToken(AsmToken::LessGreater, - StringRef(TokStart, 2)); - default: return AsmToken(AsmToken::Less, StringRef(TokStart, 1)); + case '<': + ++CurPtr; + return AsmToken(AsmToken::LessLess, StringRef(TokStart, 2)); + case '=': + ++CurPtr; + return AsmToken(AsmToken::LessEqual, StringRef(TokStart, 2)); + case '>': + ++CurPtr; + return AsmToken(AsmToken::LessGreater, StringRef(TokStart, 2)); + default: + return AsmToken(AsmToken::Less, StringRef(TokStart, 1)); } case '>': switch (*CurPtr) { - case '>': return ++CurPtr, AsmToken(AsmToken::GreaterGreater, - StringRef(TokStart, 2)); - case '=': return ++CurPtr, AsmToken(AsmToken::GreaterEqual, - StringRef(TokStart, 2)); - default: return AsmToken(AsmToken::Greater, StringRef(TokStart, 1)); + case '>': + ++CurPtr; + return AsmToken(AsmToken::GreaterGreater, StringRef(TokStart, 2)); + case '=': + ++CurPtr; + return AsmToken(AsmToken::GreaterEqual, StringRef(TokStart, 2)); + default: + return AsmToken(AsmToken::Greater, StringRef(TokStart, 1)); } // TODO: Quoted identifiers (objc methods etc) diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp index 19b8221..744506c 100644 --- a/llvm/lib/Support/APFloat.cpp +++ b/llvm/lib/Support/APFloat.cpp @@ -501,7 +501,9 @@ powerOf5(integerPart *dst, unsigned int power) /* Now result is in p1 with partsCount parts and p2 is scratch space. */ - tmp = p1, p1 = p2, p2 = tmp; + tmp = p1; + p1 = p2; + p2 = tmp; } pow5 += pc; diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index be1b556..83455f6 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -2698,8 +2698,10 @@ APInt::tcDivide(integerPart *lhs, const integerPart *rhs, break; shiftCount--; tcShiftRight(srhs, parts, 1); - if ((mask >>= 1) == 0) - mask = (integerPart) 1 << (integerPartWidth - 1), n--; + if ((mask >>= 1) == 0) { + mask = (integerPart) 1 << (integerPartWidth - 1); + n--; + } } return false; diff --git a/llvm/lib/Support/FileUtilities.cpp b/llvm/lib/Support/FileUtilities.cpp index 5316f04..c6a58cc 100644 --- a/llvm/lib/Support/FileUtilities.cpp +++ b/llvm/lib/Support/FileUtilities.cpp @@ -217,8 +217,10 @@ int llvm::DiffFilesWithTolerance(StringRef NameA, bool CompareFailed = false; while (1) { // Scan for the end of file or next difference. - while (F1P < File1End && F2P < File2End && *F1P == *F2P) - ++F1P, ++F2P; + while (F1P < File1End && F2P < File2End && *F1P == *F2P) { + ++F1P; + ++F2P; + } if (F1P >= File1End || F2P >= File2End) break; diff --git a/llvm/lib/Support/IntEqClasses.cpp b/llvm/lib/Support/IntEqClasses.cpp index ff21357..cb6e3a1 100644 --- a/llvm/lib/Support/IntEqClasses.cpp +++ b/llvm/lib/Support/IntEqClasses.cpp @@ -37,10 +37,15 @@ unsigned IntEqClasses::join(unsigned a, unsigned b) { // incrementally. The larger leader will eventually be updated, joining the // classes. while (eca != ecb) - if (eca < ecb) - EC[b] = eca, b = ecb, ecb = EC[b]; - else - EC[a] = ecb, a = eca, eca = EC[a]; + if (eca < ecb) { + EC[b] = eca; + b = ecb; + ecb = EC[b]; + } else { + EC[a] = ecb; + a = eca; + eca = EC[a]; + } return eca; } diff --git a/llvm/lib/Support/Unix/Process.inc b/llvm/lib/Support/Unix/Process.inc index 27083ee..cad81f8 100644 --- a/llvm/lib/Support/Unix/Process.inc +++ b/llvm/lib/Support/Unix/Process.inc @@ -456,7 +456,7 @@ unsigned llvm::sys::Process::GetRandomNumber() { #if defined(HAVE_DECL_ARC4RANDOM) && HAVE_DECL_ARC4RANDOM return arc4random(); #else - static int x = (::srand(GetRandomNumberSeed()), 0); + static int x = (static_cast(::srand(GetRandomNumberSeed())), 0); (void)x; return ::rand(); #endif diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 0395c48..29ddd6f 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1880,39 +1880,45 @@ void AArch64InstrInfo::storeRegToStackSlot( else if (AArch64::DDRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register store without NEON"); - Opc = AArch64::ST1Twov1d, Offset = false; + Opc = AArch64::ST1Twov1d; + Offset = false; } break; case 24: if (AArch64::DDDRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register store without NEON"); - Opc = AArch64::ST1Threev1d, Offset = false; + Opc = AArch64::ST1Threev1d; + Offset = false; } break; case 32: if (AArch64::DDDDRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register store without NEON"); - Opc = AArch64::ST1Fourv1d, Offset = false; + Opc = AArch64::ST1Fourv1d; + Offset = false; } else if (AArch64::QQRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register store without NEON"); - Opc = AArch64::ST1Twov2d, Offset = false; + Opc = AArch64::ST1Twov2d; + Offset = false; } break; case 48: if (AArch64::QQQRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register store without NEON"); - Opc = AArch64::ST1Threev2d, Offset = false; + Opc = AArch64::ST1Threev2d; + Offset = false; } break; case 64: if (AArch64::QQQQRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register store without NEON"); - Opc = AArch64::ST1Fourv2d, Offset = false; + Opc = AArch64::ST1Fourv2d; + Offset = false; } break; } @@ -1978,39 +1984,45 @@ void AArch64InstrInfo::loadRegFromStackSlot( else if (AArch64::DDRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register load without NEON"); - Opc = AArch64::LD1Twov1d, Offset = false; + Opc = AArch64::LD1Twov1d; + Offset = false; } break; case 24: if (AArch64::DDDRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register load without NEON"); - Opc = AArch64::LD1Threev1d, Offset = false; + Opc = AArch64::LD1Threev1d; + Offset = false; } break; case 32: if (AArch64::DDDDRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register load without NEON"); - Opc = AArch64::LD1Fourv1d, Offset = false; + Opc = AArch64::LD1Fourv1d; + Offset = false; } else if (AArch64::QQRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register load without NEON"); - Opc = AArch64::LD1Twov2d, Offset = false; + Opc = AArch64::LD1Twov2d; + Offset = false; } break; case 48: if (AArch64::QQQRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register load without NEON"); - Opc = AArch64::LD1Threev2d, Offset = false; + Opc = AArch64::LD1Threev2d; + Offset = false; } break; case 64: if (AArch64::QQQQRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasNEON() && "Unexpected register load without NEON"); - Opc = AArch64::LD1Fourv2d, Offset = false; + Opc = AArch64::LD1Fourv2d; + Offset = false; } break; } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 1eaa811..7e8fc309 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -3565,11 +3565,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(0), MachineNode->getOperand(1). getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(0), - MachineNode->getOperand(1)), + MachineNode->getOperand(1)); SelectSwap = true; + } break; case PPC::CRNAND: if (MachineNode->getOperand(0) == MachineNode->getOperand(1)) @@ -3603,11 +3604,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(1). getOperand(0), MachineNode->getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(0), - MachineNode->getOperand(1)), + MachineNode->getOperand(1)); SelectSwap = true; + } break; case PPC::CROR: if (MachineNode->getOperand(0) == MachineNode->getOperand(1)) @@ -3635,11 +3637,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(0), MachineNode->getOperand(1). getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(0), - MachineNode->getOperand(1)), + MachineNode->getOperand(1)); SelectSwap = true; + } break; case PPC::CRXOR: if (MachineNode->getOperand(0) == MachineNode->getOperand(1)) @@ -3674,11 +3677,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(0), MachineNode->getOperand(1). getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(0), - MachineNode->getOperand(1)), + MachineNode->getOperand(1)); SelectSwap = true; + } break; case PPC::CRNOR: if (Op1Set || Op2Set) @@ -3707,11 +3711,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(1). getOperand(0), MachineNode->getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(0), - MachineNode->getOperand(1)), + MachineNode->getOperand(1)); SelectSwap = true; + } break; case PPC::CREQV: if (MachineNode->getOperand(0) == MachineNode->getOperand(1)) @@ -3746,11 +3751,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(0), MachineNode->getOperand(1). getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(0), - MachineNode->getOperand(1)), + MachineNode->getOperand(1)); SelectSwap = true; + } break; case PPC::CRANDC: if (MachineNode->getOperand(0) == MachineNode->getOperand(1)) @@ -3781,11 +3787,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(0), MachineNode->getOperand(1). getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(1), - MachineNode->getOperand(0)), + MachineNode->getOperand(0)); SelectSwap = true; + } break; case PPC::CRORC: if (MachineNode->getOperand(0) == MachineNode->getOperand(1)) @@ -3816,11 +3823,12 @@ void PPCDAGToDAGISel::PeepholeCROps() { MVT::i1, MachineNode->getOperand(0), MachineNode->getOperand(1). getOperand(0)); - else if (AllUsersSelectZero(MachineNode)) + else if (AllUsersSelectZero(MachineNode)) { ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode), MVT::i1, MachineNode->getOperand(1), - MachineNode->getOperand(0)), + MachineNode->getOperand(0)); SelectSwap = true; + } break; case PPC::SELECT_I4: case PPC::SELECT_I8: diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 149cc4d..5073942 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -883,8 +883,8 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (PPC::CRBITRCRegClass.contains(SrcReg) && PPC::GPRCRegClass.contains(DestReg)) { unsigned CRReg = getCRFromCRBit(SrcReg); - BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg) - .addReg(CRReg), getKillRegState(KillSrc); + BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); + getKillRegState(KillSrc); // Rotate the CR bit in the CR fields to be the least significant bit and // then mask with 0x1 (MB = ME = 31). BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) @@ -895,13 +895,13 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } else if (PPC::CRRCRegClass.contains(SrcReg) && PPC::G8RCRegClass.contains(DestReg)) { - BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg) - .addReg(SrcReg), getKillRegState(KillSrc); + BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg); + getKillRegState(KillSrc); return; } else if (PPC::CRRCRegClass.contains(SrcReg) && PPC::GPRCRegClass.contains(DestReg)) { - BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg) - .addReg(SrcReg), getKillRegState(KillSrc); + BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg); + getKillRegState(KillSrc); return; } diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 97bb8ab..3718ac5 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -1542,7 +1542,8 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { // Remove the operand so that later passes don't see it. MI->RemoveOperand(i); - --i, --e; + --i; + --e; } // We may have been carrying spurious live-ins, so make sure only the returned diff --git a/llvm/lib/Transforms/IPO/MergeFunctions.cpp b/llvm/lib/Transforms/IPO/MergeFunctions.cpp index 702aaa9..2030c22 100644 --- a/llvm/lib/Transforms/IPO/MergeFunctions.cpp +++ b/llvm/lib/Transforms/IPO/MergeFunctions.cpp @@ -1186,7 +1186,8 @@ int FunctionComparator::cmpBasicBlocks(const BasicBlock *BBL, } } - ++InstL, ++InstR; + ++InstL; + ++InstR; } while (InstL != InstLE && InstR != InstRE); if (InstL != InstLE && InstR == InstRE) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index e7e3f82..9e3cf30 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -123,11 +123,18 @@ namespace { bool isConstant() const { return Val == nullptr; } bool isZero() const { return Coeff.isZero(); } - void set(short Coefficient, Value *V) { Coeff.set(Coefficient), Val = V; } - void set(const APFloat& Coefficient, Value *V) - { Coeff.set(Coefficient); Val = V; } - void set(const ConstantFP* Coefficient, Value *V) - { Coeff.set(Coefficient->getValueAPF()); Val = V; } + void set(short Coefficient, Value *V) { + Coeff.set(Coefficient); + Val = V; + } + void set(const APFloat &Coefficient, Value *V) { + Coeff.set(Coefficient); + Val = V; + } + void set(const ConstantFP *Coefficient, Value *V) { + Coeff.set(Coefficient->getValueAPF()); + Val = V; + } void negate() { Coeff.negate(); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index 7784274..2904da0 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -2473,7 +2473,8 @@ InstCombiner::transformCallThroughTrampoline(CallSite CS, Idx + (Idx >= NestIdx), B)); } - ++Idx, ++I; + ++Idx; + ++I; } while (1); } @@ -2507,7 +2508,8 @@ InstCombiner::transformCallThroughTrampoline(CallSite CS, // Add the original type. NewTypes.push_back(*I); - ++Idx, ++I; + ++Idx; + ++I; } while (1); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 1e6e072..6ee0525 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -3674,10 +3674,14 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { // Analyze the case when either Op0 or Op1 is an add instruction. // Op0 = A + B (or A and B are null); Op1 = C + D (or C and D are null). Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr; - if (BO0 && BO0->getOpcode() == Instruction::Add) - A = BO0->getOperand(0), B = BO0->getOperand(1); - if (BO1 && BO1->getOpcode() == Instruction::Add) - C = BO1->getOperand(0), D = BO1->getOperand(1); + if (BO0 && BO0->getOpcode() == Instruction::Add) { + A = BO0->getOperand(0); + B = BO0->getOperand(1); + } + if (BO1 && BO1->getOpcode() == Instruction::Add) { + C = BO1->getOperand(0); + D = BO1->getOperand(1); + } // icmp (X+cst) < 0 --> X < -cst if (NoOp0WrapProblem && ICmpInst::isSigned(Pred) && match(Op1, m_Zero())) @@ -3794,11 +3798,18 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { // Analyze the case when either Op0 or Op1 is a sub instruction. // Op0 = A - B (or A and B are null); Op1 = C - D (or C and D are null). - A = nullptr; B = nullptr; C = nullptr; D = nullptr; - if (BO0 && BO0->getOpcode() == Instruction::Sub) - A = BO0->getOperand(0), B = BO0->getOperand(1); - if (BO1 && BO1->getOpcode() == Instruction::Sub) - C = BO1->getOperand(0), D = BO1->getOperand(1); + A = nullptr; + B = nullptr; + C = nullptr; + D = nullptr; + if (BO0 && BO0->getOpcode() == Instruction::Sub) { + A = BO0->getOperand(0); + B = BO0->getOperand(1); + } + if (BO1 && BO1->getOpcode() == Instruction::Sub) { + C = BO1->getOperand(0); + D = BO1->getOperand(1); + } // icmp (X-Y), X -> icmp 0, Y for equalities or if there is no overflow. if (A == Op1 && NoOp0WrapProblem) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 6a7e29b..4c3dccb 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -374,10 +374,13 @@ Instruction *InstCombiner::visitMul(BinaryOperator &I) { APInt Negative2(I.getType()->getPrimitiveSizeInBits(), (uint64_t)-2, true); Value *BoolCast = nullptr, *OtherOp = nullptr; - if (MaskedValueIsZero(Op0, Negative2, 0, &I)) - BoolCast = Op0, OtherOp = Op1; - else if (MaskedValueIsZero(Op1, Negative2, 0, &I)) - BoolCast = Op1, OtherOp = Op0; + if (MaskedValueIsZero(Op0, Negative2, 0, &I)) { + BoolCast = Op0; + OtherOp = Op1; + } else if (MaskedValueIsZero(Op1, Negative2, 0, &I)) { + BoolCast = Op1; + OtherOp = Op0; + } if (BoolCast) { Value *V = Builder->CreateSub(Constant::getNullValue(I.getType()), diff --git a/llvm/lib/Transforms/Scalar/Sink.cpp b/llvm/lib/Transforms/Scalar/Sink.cpp index 64109b2..eb09f58 100644 --- a/llvm/lib/Transforms/Scalar/Sink.cpp +++ b/llvm/lib/Transforms/Scalar/Sink.cpp @@ -145,8 +145,10 @@ bool Sinking::ProcessBlock(BasicBlock &BB) { if (isa(Inst)) continue; - if (SinkInstruction(Inst, Stores)) - ++NumSunk, MadeChange = true; + if (SinkInstruction(Inst, Stores)) { + ++NumSunk; + MadeChange = true; + } // If we just processed the first instruction in the block, we're done. } while (!ProcessedBegin); diff --git a/llvm/lib/Transforms/Utils/CloneFunction.cpp b/llvm/lib/Transforms/Utils/CloneFunction.cpp index 8b5692a..05b0a17 100644 --- a/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -529,7 +529,8 @@ void llvm::CloneAndPruneIntoFromInst(Function *NewFunc, const Function *OldFunc, PN->setIncomingBlock(pred, MappedBlock); } else { PN->removeIncomingValue(pred, false); - --pred, --e; // Revisit the next entry. + --pred; // Revisit the next entry. + --e; } } } diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp index c4f9b9f..fba09e1 100644 --- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp +++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp @@ -802,7 +802,8 @@ void PromoteMem2Reg::ComputeLiveInBlocks( // actually live-in here. LiveInBlockWorklist[i] = LiveInBlockWorklist.back(); LiveInBlockWorklist.pop_back(); - --i, --e; + --i; + --e; break; } diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 3c83172..66c6944 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -2190,16 +2190,19 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, unsigned BonusInstThreshold) { bool InvertPredCond = false; if (BI->isConditional()) { - if (PBI->getSuccessor(0) == TrueDest) + if (PBI->getSuccessor(0) == TrueDest) { Opc = Instruction::Or; - else if (PBI->getSuccessor(1) == FalseDest) + } else if (PBI->getSuccessor(1) == FalseDest) { Opc = Instruction::And; - else if (PBI->getSuccessor(0) == FalseDest) - Opc = Instruction::And, InvertPredCond = true; - else if (PBI->getSuccessor(1) == TrueDest) - Opc = Instruction::Or, InvertPredCond = true; - else + } else if (PBI->getSuccessor(0) == FalseDest) { + Opc = Instruction::And; + InvertPredCond = true; + } else if (PBI->getSuccessor(1) == TrueDest) { + Opc = Instruction::Or; + InvertPredCond = true; + } else { continue; + } } else { if (PBI->getSuccessor(0) != TrueDest && PBI->getSuccessor(1) != TrueDest) continue; @@ -2750,16 +2753,21 @@ static bool SimplifyCondBranchToCondBranch(BranchInst *PBI, BranchInst *BI, return false; int PBIOp, BIOp; - if (PBI->getSuccessor(0) == BI->getSuccessor(0)) - PBIOp = BIOp = 0; - else if (PBI->getSuccessor(0) == BI->getSuccessor(1)) - PBIOp = 0, BIOp = 1; - else if (PBI->getSuccessor(1) == BI->getSuccessor(0)) - PBIOp = 1, BIOp = 0; - else if (PBI->getSuccessor(1) == BI->getSuccessor(1)) - PBIOp = BIOp = 1; - else + if (PBI->getSuccessor(0) == BI->getSuccessor(0)) { + PBIOp = 0; + BIOp = 0; + } else if (PBI->getSuccessor(0) == BI->getSuccessor(1)) { + PBIOp = 0; + BIOp = 1; + } else if (PBI->getSuccessor(1) == BI->getSuccessor(0)) { + PBIOp = 1; + BIOp = 0; + } else if (PBI->getSuccessor(1) == BI->getSuccessor(1)) { + PBIOp = 1; + BIOp = 1; + } else { return false; + } // Check to make sure that the other destination of this branch // isn't BB itself. If so, this is an infinite loop that will diff --git a/llvm/tools/llvm-diff/DifferenceEngine.cpp b/llvm/tools/llvm-diff/DifferenceEngine.cpp index 456560b..fc9ea99 100644 --- a/llvm/tools/llvm-diff/DifferenceEngine.cpp +++ b/llvm/tools/llvm-diff/DifferenceEngine.cpp @@ -210,7 +210,8 @@ class FunctionDifferenceEngine { if (!LeftI->use_empty()) TentativeValues.insert(std::make_pair(LeftI, RightI)); - ++LI, ++RI; + ++LI; + ++RI; } while (LI != LE); // This is sufficient: we can't get equality of // terminators if there are residual instructions. @@ -555,7 +556,9 @@ void FunctionDifferenceEngine::runBlockDiff(BasicBlock::iterator LStart, PI = Path.begin(), PE = Path.end(); while (PI != PE && *PI == DC_match) { unify(&*LI, &*RI); - ++PI, ++LI, ++RI; + ++PI; + ++LI; + ++RI; } for (; PI != PE; ++PI) { @@ -589,7 +592,8 @@ void FunctionDifferenceEngine::runBlockDiff(BasicBlock::iterator LStart, while (LI != LE) { assert(RI != RE); unify(&*LI, &*RI); - ++LI, ++RI; + ++LI; + ++RI; } // If the terminators have different kinds, but one is an invoke and the diff --git a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp index 650955d..76387c7 100644 --- a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp +++ b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp @@ -247,7 +247,7 @@ bool Decoder::opcode_10Lxxxxx(const uint8_t *OC, unsigned &Offset, printRegisters(std::make_pair(RegisterMask, 0)); OS << '\n'; - ++Offset, ++Offset; + Offset += 2; return false; } @@ -320,7 +320,7 @@ bool Decoder::opcode_111010xx(const uint8_t *OC, unsigned &Offset, static_cast(Prologue ? "sub" : "add"), Imm); - ++Offset, ++Offset; + Offset += 2; return false; } @@ -334,7 +334,7 @@ bool Decoder::opcode_1110110L(const uint8_t *OC, unsigned &Offset, printRegisters(std::make_pair(GPRMask, 0)); OS << '\n'; - ++Offset, ++Offset; + Offset += 2; return false; } @@ -350,7 +350,7 @@ bool Decoder::opcode_11101110(const uint8_t *OC, unsigned &Offset, << format("0x%02x 0x%02x ; microsoft-specific (type: %u)\n", OC[Offset + 0], OC[Offset + 1], OC[Offset + 1] & 0x0f); - ++Offset, ++Offset; + Offset += 2; return false; } @@ -366,7 +366,7 @@ bool Decoder::opcode_11101111(const uint8_t *OC, unsigned &Offset, << format("0x%02x 0x%02x ; ldr.w lr, [sp], #%u\n", OC[Offset + 0], OC[Offset + 1], OC[Offset + 1] << 2); - ++Offset, ++Offset; + Offset += 2; return false; } @@ -381,7 +381,7 @@ bool Decoder::opcode_11110101(const uint8_t *OC, unsigned &Offset, printRegisters(std::make_pair(0, VFPMask)); OS << '\n'; - ++Offset, ++Offset; + Offset += 2; return false; } @@ -396,7 +396,7 @@ bool Decoder::opcode_11110110(const uint8_t *OC, unsigned &Offset, printRegisters(std::make_pair(0, VFPMask)); OS << '\n'; - ++Offset, ++Offset; + Offset += 2; return false; } @@ -409,7 +409,7 @@ bool Decoder::opcode_11110111(const uint8_t *OC, unsigned &Offset, static_cast(Prologue ? "sub" : "add"), Imm); - ++Offset, ++Offset, ++Offset; + Offset += 3; return false; } @@ -424,7 +424,7 @@ bool Decoder::opcode_11111000(const uint8_t *OC, unsigned &Offset, OC[Offset + 0], OC[Offset + 1], OC[Offset + 2], OC[Offset + 3], static_cast(Prologue ? "sub" : "add"), Imm); - ++Offset, ++Offset, ++Offset, ++Offset; + Offset += 4; return false; } @@ -437,7 +437,7 @@ bool Decoder::opcode_11111001(const uint8_t *OC, unsigned &Offset, OC[Offset + 0], OC[Offset + 1], OC[Offset + 2], static_cast(Prologue ? "sub" : "add"), Imm); - ++Offset, ++Offset, ++Offset; + Offset += 3; return false; } @@ -452,7 +452,7 @@ bool Decoder::opcode_11111010(const uint8_t *OC, unsigned &Offset, OC[Offset + 0], OC[Offset + 1], OC[Offset + 2], OC[Offset + 3], static_cast(Prologue ? "sub" : "add"), Imm); - ++Offset, ++Offset, ++Offset, ++Offset; + Offset += 4; return false; } -- 2.7.4