From 79aa4af078c8c089c1973dc8444f79bb46774f43 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@collabora.com>
Date: Wed, 2 Mar 2022 18:58:39 -0500
Subject: [PATCH] pan/va: Remap "store segment" to "memory access"

For now, the difference does not matter. However it's better to model the actual
hardware behaviour, rather than isomorphic driver behaviour, when we can do so.
So fix the names.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
---
 src/panfrost/bifrost/valhall/ISA.xml                  | 14 +++++++-------
 src/panfrost/bifrost/valhall/test/assembler-cases.txt |  4 ++--
 src/panfrost/bifrost/valhall/valhall.py               |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index 6c8a67b..ce6c515 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -593,12 +593,12 @@
     <value desc="Slot #7">slot7</value>
   </enum>
 
-  <enum name="Store segment">
-    <desc>Memory segment written to by a `STORE` instruction.</desc>
-    <value desc="Global or workgroup local memory" default="none">global</value>
-    <value desc="Position output (in a position shader)">pos</value>
-    <value desc="Varyings with LEA_VARY computed addresses">vary</value>
-    <value desc="Thread local storage">tl</value>
+  <enum name="Memory access">
+    <desc>Memory access hint for a `LOAD` or `STORE` instruction.</desc>
+    <value desc="No hint (global)" default="true">none</value>
+    <value desc="Internally streaming (position output)">istream</value>
+    <value desc="Externally streaming (varying output)">estream</value>
+    <value desc="Force access in discarded threads (thread local storage)">force</value>
   </enum>
 
   <enum name="Subgroup size">
@@ -1123,7 +1123,7 @@
     <ins name="STORE.i96" opcode2="0x6"/>
     <ins name="STORE.i128" opcode2="0x7"/>
     <sr_count/>
-    <store_segment/>
+    <memory_access/>
     <slot/>
     <src>Address to store to after adding offset</src>
     <imm name="offset" start="8" size="16" signed="true"/>
diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
index 73c3361..60cffc9 100644
--- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
@@ -55,8 +55,8 @@ f0 00 3c 33 04 40 7f 78    BLEND.slot0.v4.f16.return @r0:r1, @r60, blend_descrip
 00 dd c0 08 14 c2 b2 00    FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
 41 88 c0 00 04 c1 b2 00    FMA.f32 r1, `r1, u8, 0x0.neg
 40 88 c0 00 04 c0 b2 10    FMA.f32.wait1 r0, `r0, u8, 0x0.neg
-44 00 00 32 06 40 61 78    STORE.i96.vary.slot0.return @r0:r1:r2, `r4, offset:0
-44 00 00 39 08 48 61 78    STORE.i128.pos.slot0.return @r8:r9:r10:r11, `r4, offset:0
+44 00 00 32 06 40 61 78    STORE.i96.estream.slot0.return @r0:r1:r2, `r4, offset:0
+44 00 00 39 08 48 61 78    STORE.i128.istream.slot0.return @r8:r9:r10:r11, `r4, offset:0
 00 00 00 c0 01 c0 45 48    BARRIER.slot7.barrier 
 80 00 00 00 82 82 60 00    LOAD.i8.unsigned.slot0 @r2, u0, offset:0
 80 00 00 08 82 82 60 00    LOAD.i16.unsigned.slot0 @r2, u0, offset:0
diff --git a/src/panfrost/bifrost/valhall/valhall.py b/src/panfrost/bifrost/valhall/valhall.py
index b753f92..757149b 100644
--- a/src/panfrost/bifrost/valhall/valhall.py
+++ b/src/panfrost/bifrost/valhall/valhall.py
@@ -360,7 +360,7 @@ MODIFIERS = {
     "secondary_register_width": Modifier("secondary_register_width", 47, 1, force_enum = "register_width"),
 
     "inactive_result": Modifier("inactive_result", 22, 4),
-    "store_segment": Modifier("store_segment", 24, 2),
+    "memory_access": Modifier("memory_access", 24, 2),
     "regfmt": Modifier("register_format", 24, 3),
     "source_format": Modifier("source_format", 24, 4),
     "vecsize": Modifier("vector_size", 28, 2),
-- 
2.7.4