From 798b6419bc8446ba4d30c61e182ec628ea44ce40 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Mon, 19 Jun 2023 15:35:48 +0100 Subject: [PATCH] [LSR] Add test for for issue leading to revert of abfeda5af329b5. Add unit test triggering an assertion with abfeda5af329b5. --- .../postinc-with-fixups-with-different-loops.ll | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 llvm/test/Transforms/LoopStrengthReduce/AArch64/postinc-with-fixups-with-different-loops.ll diff --git a/llvm/test/Transforms/LoopStrengthReduce/AArch64/postinc-with-fixups-with-different-loops.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/postinc-with-fixups-with-different-loops.ll new file mode 100644 index 0000000..60d5588 --- /dev/null +++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/postinc-with-fixups-with-different-loops.ll @@ -0,0 +1,53 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt -loop-reduce -S %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx13.0.0" + +declare void @use(i32) + +define i32 @test() { +; CHECK-LABEL: define i32 @test() { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP_1:%.*]] +; CHECK: loop.1: +; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[LOOP_1]] ], [ -1, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 1 +; CHECK-NEXT: br i1 false, label [[LOOP_2_PH:%.*]], label [[LOOP_1]] +; CHECK: loop.2.ph: +; CHECK-NEXT: [[LSR_IV_NEXT2_LCSSA:%.*]] = phi i32 [ [[LSR_IV_NEXT2]], [[LOOP_1]] ] +; CHECK-NEXT: br label [[LOOP_2:%.*]] +; CHECK: loop.2: +; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP_2]] ], [ 1, [[LOOP_2_PH]] ] +; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[LSR_IV_NEXT2_LCSSA]], [[LOOP_2_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_2]] ] +; CHECK-NEXT: call void @use(i32 [[IV_2]]) +; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0 +; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_2]] +; CHECK: exit: +; CHECK-NEXT: ret i32 [[IV_2_NEXT]] +; +entry: + br label %loop.1 + +loop.1: + %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1 ] + %iv.1.next = add i32 %iv.1, 1 + br i1 false, label %loop.2.ph, label %loop.1 + +loop.2.ph: + br label %loop.2 + +loop.2: + %iv.2 = phi i32 [ %iv.1, %loop.2.ph ], [ %iv.2.next, %loop.2 ] + %iv.3 = phi i64 [ 0, %loop.2.ph ], [ %iv.3.next, %loop.2 ] + call void @use(i32 %iv.2) + %iv.2.next = add i32 %iv.2, 1 + %iv.3.next = add i64 %iv.3, 1 + %ec = icmp eq i64 %iv.3, 0 + br i1 %ec, label %exit, label %loop.2 + +exit: + ret i32 %iv.2.next +} -- 2.7.4