From 78e4b2be0335da971b70f75297f2db2eeed5ec6a Mon Sep 17 00:00:00 2001 From: Pan Gao Date: Wed, 3 Aug 2022 20:48:18 +0800 Subject: [PATCH] Fix memory barrier for alias sparse memory Memory read/write order through different views that are aliased need to be handled in application. Otherwise, implementation may give undefined results. Affects: dEQP-VK.sparse_resources.image_sparse_memory_aliasing.* Components: Vulkan VK-GL-CTS issue: 3709 Change-Id: I8739aeeaf05103942158451196480734f62ab835 --- .../vulkan/sparse_resources/vktSparseResourcesImageMemoryAliasing.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/external/vulkancts/modules/vulkan/sparse_resources/vktSparseResourcesImageMemoryAliasing.cpp b/external/vulkancts/modules/vulkan/sparse_resources/vktSparseResourcesImageMemoryAliasing.cpp index f465a93..e946c47 100755 --- a/external/vulkancts/modules/vulkan/sparse_resources/vktSparseResourcesImageMemoryAliasing.cpp +++ b/external/vulkancts/modules/vulkan/sparse_resources/vktSparseResourcesImageMemoryAliasing.cpp @@ -598,7 +598,7 @@ tcu::TestStatus ImageSparseMemoryAliasingInstance::iterate (void) )); } - deviceInterface.cmdPipelineBarrier(*commandBuffer, VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, 0u, 0u, DE_NULL, 0u, DE_NULL, static_cast(imageSparseShaderStorageBarriers.size()), imageSparseShaderStorageBarriers.data()); + deviceInterface.cmdPipelineBarrier(*commandBuffer, VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, 0u, 0u, DE_NULL, 0u, DE_NULL, static_cast(imageSparseShaderStorageBarriers.size()), imageSparseShaderStorageBarriers.data()); } // Create descriptor set layout -- 2.7.4