From 78833a43e8d84e9650faa28ef8ee4517fbd7a11b Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Tue, 20 Sep 2022 00:21:55 +0100 Subject: [PATCH] [GlobalISel][Legalizer] Fix lowerSelect() not sign-extending the mask value. I'm not sure why the SEXT_INREG was gated on a bitwidth check of the mask vs element size. This fixes a miscompile in chromium's skia library. Differential Revision: https://reviews.llvm.org/D134236 --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 4 +--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir | 3 ++- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 2a45cff..2b9bc22 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -7247,10 +7247,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { // The condition was potentially zero extended before, but we want a sign // extended boolean. - if (MaskTy.getSizeInBits() <= DstTy.getScalarSizeInBits() && - MaskTy != LLT::scalar(1)) { + if (MaskTy != LLT::scalar(1)) MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0); - } // Continue the sign extension (or truncate) to match the data type. MaskElt = MIRBuilder.buildSExtOrTrunc(DstTy.getElementType(), diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir index b1517de..b0abdb9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir @@ -307,7 +307,8 @@ body: | ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32) ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %w0(s32), [[C]] ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT %cmp(s1) - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ZEXT]](s32) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXT]], 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[SEXT_INREG]](s32) ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s1>) = G_IMPLICIT_DEF ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C2]](s64) -- 2.7.4