From 788068912fd9d10f8d5cc3b6e07ff6338e7a1d8c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 25 May 2016 09:06:29 +0200
Subject: [PATCH] arm64: mvebu: Armada 7K/8K: Add COMPHY device tree nodes

This patch adds the COMPHY device tree nodes that are still missing to
the Armada 7K/8K dts files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
---
 arch/arm/dts/armada-7040-db.dts       | 40 +++++++++++++++++++++++++++++++++++
 arch/arm/dts/armada-cp110-master.dtsi | 28 ++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 070b589..df0c327 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -146,3 +146,43 @@
 &cpm_usb3_1 {
 	status = "okay";
 };
+
+&comphy_cp110 {
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_SGMII0>;
+		phy-speed = <PHY_SPEED_1_25G>;
+	};
+
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy4 {
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&utmi0 {
+	status = "okay";
+};
+
+&utmi1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 367138b..7da98bf 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -44,6 +44,8 @@
  * Device Tree file for Marvell Armada CP110 Master.
  */
 
+#include <dt-bindings/comphy/comphy_data.h>
+
 / {
 	cp110-master {
 		#address-cells = <2>;
@@ -146,6 +148,32 @@
 				clocks = <&cpm_syscon0 1 21>;
 				status = "disabled";
 			};
+
+			comphy_cp110: comphy@441000 {
+				compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+				reg = <0x441000 0x8>,
+				      <0x120000 0x8>;
+				mux-bitcount = <4>;
+				max-lanes = <6>;
+			};
+
+			utmi0: utmi@580000 {
+				compatible = "marvell,mvebu-utmi-2.6.0";
+				reg = <0x580000 0x1000>,	/* utmi-unit */
+				      <0x440420 0x4>,		/* usb-cfg */
+				      <0x440440 0x4>;		/* utmi-cfg */
+				utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+				status = "disabled";
+			};
+
+			utmi1: utmi@581000 {
+				compatible = "marvell,mvebu-utmi-2.6.0";
+				reg = <0x581000 0x1000>,	/* utmi-unit */
+				      <0x440420 0x4>,		/* usb-cfg */
+				      <0x440444 0x4>;		/* utmi-cfg */
+				utmi-port = <UTMI_PHY_TO_USB_HOST1>;
+				status = "disabled";
+			};
 		};
 
 		cpm_pcie0: pcie@f2600000 {
-- 
2.7.4