From 7868c8698f47c465004db9a5b612166633cb10ca Mon Sep 17 00:00:00 2001 From: Mark Janes Date: Thu, 1 Jun 2023 09:18:28 -0700 Subject: [PATCH] iris: convert Wa_14010455700 to use workaround mechanism MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The original lineage for 14010455700 is 1808121037. Use this defect number to apply the workaround to relevant platforms with the new workaround mechanism. Reviewed-by: Nanley Chery Reviewed-by: José Roberto de Souza Part-of: --- src/gallium/drivers/iris/iris_state.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index cf1abf8..53b5ad2 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1360,7 +1360,7 @@ struct iris_depth_buffer_state { GENX(3DSTATE_CLEAR_PARAMS_length)]; }; -#if GFX_VERx10 == 120 +#if INTEL_NEEDS_WA_1808121037 enum iris_depth_reg_mode { IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0, IRIS_DEPTH_REG_MODE_D16_1X_MSAA, @@ -1389,7 +1389,7 @@ struct iris_genx_state { /* Is object level preemption enabled? */ bool object_preemption; -#if GFX_VERx10 == 120 +#if INTEL_NEEDS_WA_1808121037 enum iris_depth_reg_mode depth_reg_mode; #endif @@ -6069,7 +6069,7 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice, struct iris_batch *batch, const struct isl_surf *surf) { -#if GFX_VERx10 == 120 +#if INTEL_NEEDS_WA_1808121037 const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM && surf->samples == 1; @@ -6091,11 +6091,11 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice, * settings while we change the registers. */ iris_emit_end_of_pipe_sync(batch, - "Workaround: Stop pipeline for 14010455700", + "Workaround: Stop pipeline for Wa_1808121037", PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_DEPTH_CACHE_FLUSH); - /* Wa_14010455700 + /* Wa_1808121037 * * To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer * Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”. @@ -8813,7 +8813,7 @@ iris_lost_genx_state(struct iris_context *ice, struct iris_batch *batch) { struct iris_genx_state *genx = ice->state.genx; -#if GFX_VERx10 == 120 +#if INTEL_NEEDS_WA_1808121037 genx->depth_reg_mode = IRIS_DEPTH_REG_MODE_UNKNOWN; #endif -- 2.7.4