From 78624f54126e08b382f81829ee419c20e884254d Mon Sep 17 00:00:00 2001 From: uros Date: Sat, 23 Feb 2008 15:24:02 +0000 Subject: [PATCH] PR target/22076 PR target/34256 * config/i386/mmx.md (*mov_internal_rex64): Use "!y" to prevent reload from using MMX registers. (*mov_internal): Ditto. (*movv2sf_internal_rex64): Ditto. (*movv2sf_internal): Ditto. testsuite/ChangeLog: PR target/22076 PR target/34256 * gcc.target/i386/pr22076.c: New test. * gcc.target/i386/pr34256.c: New test. * gcc.target/i386/vecinit-5.c: New test. * gcc.target/i386/vecinit-6.c: New test. * gcc.target/i386/vecinit-[1-4].c: Check that no MMX register is used. * g++.dg/compat/struct-layout-1.h: Do not include and , define __m64 and __m128 directly. * g++.dg/compat/struct-layout-1_generate.c: Add -mno-mmx for x86. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@132572 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 +++++++++ gcc/config/i386/mmx.md | 16 +++++++-------- gcc/testsuite/ChangeLog | 14 +++++++++++++ gcc/testsuite/g++.dg/compat/struct-layout-1.h | 4 ++-- .../g++.dg/compat/struct-layout-1_generate.c | 1 + gcc/testsuite/gcc.target/i386/pr22076.c | 18 ++++++++++++++++ gcc/testsuite/gcc.target/i386/pr34256.c | 14 +++++++++++++ gcc/testsuite/gcc.target/i386/vecinit-1.c | 1 + gcc/testsuite/gcc.target/i386/vecinit-2.c | 1 + gcc/testsuite/gcc.target/i386/vecinit-3.c | 1 + gcc/testsuite/gcc.target/i386/vecinit-4.c | 1 + gcc/testsuite/gcc.target/i386/vecinit-5.c | 24 ++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/vecinit-6.c | 24 ++++++++++++++++++++++ 13 files changed, 119 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr22076.c create mode 100644 gcc/testsuite/gcc.target/i386/pr34256.c create mode 100644 gcc/testsuite/gcc.target/i386/vecinit-5.c create mode 100644 gcc/testsuite/gcc.target/i386/vecinit-6.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4b2f8f8..9a90b88 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2008-02-23 Uros Bizjak + + PR target/22076 + PR target/34256 + * config/i386/mmx.md (*mov_internal_rex64): Use "!y" to + prevent reload from using MMX registers. + (*mov_internal): Ditto. + (*movv2sf_internal_rex64): Ditto. + (*movv2sf_internal): Ditto. + 2008-02-23 Ralf Wildenhues PR documentation/31569 diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index ee81993..3371161 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -63,9 +63,9 @@ (define_insn "*mov_internal_rex64" [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" - "=rm,r,*y,*y ,m ,*y,Y2,x,x ,m,r,x") + "=rm,r,!y,!y ,m ,!y,Y2,x,x ,m,r,x") (match_operand:MMXMODEI 1 "vector_move_operand" - "Cr ,m,C ,*ym,*y,Y2,*y,C,xm,x,x,r"))] + "Cr ,m,C ,!ym,!y,Y2,!y,C,xm,x,x,r"))] "TARGET_64BIT && TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -87,9 +87,9 @@ (define_insn "*mov_internal" [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" - "=*y,*y ,m ,*y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,?r ,?m") + "=!y,!y ,m ,!y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,?r ,?m") (match_operand:MMXMODEI 1 "vector_move_operand" - "C ,*ym,*y,*Y2,*y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))] + "C ,!ym,!y,*Y2,!y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -122,9 +122,9 @@ (define_insn "*movv2sf_internal_rex64" [(set (match_operand:V2SF 0 "nonimmediate_operand" - "=rm,r,*y ,*y ,m ,*y,Y2,x,x,x,m,r,x") + "=rm,r,!y ,!y ,m ,!y,Y2,x,x,x,m,r,x") (match_operand:V2SF 1 "vector_move_operand" - "Cr ,m ,C ,*ym,*y,Y2,*y,C,x,m,x,x,r"))] + "Cr ,m ,C ,!ym,!y,Y2,!y,C,x,m,x,x,r"))] "TARGET_64BIT && TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -147,9 +147,9 @@ (define_insn "*movv2sf_internal" [(set (match_operand:V2SF 0 "nonimmediate_operand" - "=*y,*y ,m,*y ,*Y2,*x,*x,*x,m ,?r ,?m") + "=!y,!y ,m,!y ,*Y2,*x,*x,*x,m ,?r ,?m") (match_operand:V2SF 1 "vector_move_operand" - "C ,*ym,*y,*Y2,*y ,C ,*x,m ,*x,irm,r"))] + "C ,!ym,!y,*Y2,!y ,C ,*x,m ,*x,irm,r"))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 378f04b..21776c4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2008-02-23 Uros Bizjak + + PR target/22076 + PR target/34256 + * gcc.target/i386/pr22076.c: New test. + * gcc.target/i386/pr34256.c: New test. + * gcc.target/i386/vecinit-5.c: New test. + * gcc.target/i386/vecinit-6.c: New test. + * gcc.target/i386/vecinit-[1-4].c: Check that no MMX register is used. + + * g++.dg/compat/struct-layout-1.h: Do not include and + , define __m64 and __m128 directly. + * g++.dg/compat/struct-layout-1_generate.c: Add -mno-mmx for x86. + 2008-02-22 Andrew Pinski PR C++/34715 diff --git a/gcc/testsuite/g++.dg/compat/struct-layout-1.h b/gcc/testsuite/g++.dg/compat/struct-layout-1.h index 69c490f..2b93a72 100644 --- a/gcc/testsuite/g++.dg/compat/struct-layout-1.h +++ b/gcc/testsuite/g++.dg/compat/struct-layout-1.h @@ -44,12 +44,12 @@ typedef int u2df; #endif #if (defined __i386__ || defined __x86_64__) && !defined SKIP_ATTRIBUTE # ifdef __MMX__ -# include +typedef int __m64 __attribute__ ((__vector_size__ (8))); # else typedef int __m64; # endif # ifdef __SSE__ -# include +typedef float __m128 __attribute__ ((__vector_size__ (16))); # else typedef int __m128; # endif diff --git a/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c b/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c index 2ac0bd6..0bb70ea 100644 --- a/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c +++ b/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c @@ -44,6 +44,7 @@ along with GCC; see the file COPYING3. If not see #define DG_OPTIONS "\ /* { dg-options \"%1$s-I%2$s\" } */\n\ +/* { dg-options \"%1$s-I%2$s -mno-mmx\" { target i?86-*-* x86_64-*-* } } */\n\ /* { dg-options \"%1$s-I%2$s -fno-common\" { target hppa*-*-hpux* } } */\n\ /* { dg-options \"%1$s-I%2$s -mno-base-addresses\" { target mmix-*-* } } */\n\ \n" diff --git a/gcc/testsuite/gcc.target/i386/pr22076.c b/gcc/testsuite/gcc.target/i386/pr22076.c new file mode 100644 index 0000000..e77b994 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr22076.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -flax-vector-conversions -mmmx" } */ + +#include + +__v8qi test () +{ + __v8qi mm0 = {1,2,3,4,5,6,7,8}; + __v8qi mm1 = {11,22,33,44,55,66,77,88}; + volatile __m64 x; + + x = _mm_add_pi8 (mm0, mm1); + + return x; +} + +/* { dg-final { scan-assembler-times "movq" 3 } } */ +/* { dg-final { scan-assembler-times "movl" 1 { target ilp32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr34256.c b/gcc/testsuite/gcc.target/i386/pr34256.c new file mode 100644 index 0000000..13628ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr34256.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -march=core2" } */ + +#include + +__m64 x; +__m64 y; + +unsigned long long foo(__m64 m) { + return _mm_cvtm64_si64(_mm_add_pi32(x, y)); +} + +/* { dg-final { scan-assembler-times "mov" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vecinit-1.c b/gcc/testsuite/gcc.target/i386/vecinit-1.c index 86cad89..8553eb0 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-1.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-1.c @@ -9,3 +9,4 @@ vector float f3(void) { return (vector float){ 0.0, 0.0, a, 0.0}; } vector float f4(void) { return (vector float){ 0.0, 0.0, 0.0, a}; } /* { dg-final { scan-assembler-not "movaps" } } */ /* { dg-final { scan-assembler-not "xor" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vecinit-2.c b/gcc/testsuite/gcc.target/i386/vecinit-2.c index 41e5027..d6c715f 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-2.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-2.c @@ -9,3 +9,4 @@ vector int f3(void) { return (vector int){ 0, 0, a, 0}; } vector int f4(void) { return (vector int){ 0, 0, 0, a}; } /* { dg-final { scan-assembler-not "movaps" } } */ /* { dg-final { scan-assembler-not "xor" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vecinit-3.c b/gcc/testsuite/gcc.target/i386/vecinit-3.c index 4cbf521..053b566 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-3.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-3.c @@ -6,3 +6,4 @@ char a; vector char f(void) { return (vector char){ a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a }; } /* { dg-final { scan-assembler-not "sall" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vecinit-4.c b/gcc/testsuite/gcc.target/i386/vecinit-4.c index 7a8c1d0..773a316 100644 --- a/gcc/testsuite/gcc.target/i386/vecinit-4.c +++ b/gcc/testsuite/gcc.target/i386/vecinit-4.c @@ -5,3 +5,4 @@ short a; vector short f(void) { return (vector short){ a, a, a, a, a, a, a, a }; } /* { dg-final { scan-assembler-not "sall" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vecinit-5.c b/gcc/testsuite/gcc.target/i386/vecinit-5.c new file mode 100644 index 0000000..5764889 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vecinit-5.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +#define vector __attribute__((vector_size(16))) + +float a, b; +vector float f1(void) { return (vector float){ 0.0, 0.0, a, a}; } +vector float f2(void) { return (vector float){ a, a, 0.0, 0.0}; } +vector float f3(void) { return (vector float){ 0.0, a, 0.0, a}; } +vector float f4(void) { return (vector float){ a, 0.0, a, 0.0}; } + +vector float f5(void) { return (vector float){ 1.0, 1.0, a, a}; } +vector float f6(void) { return (vector float){ a, a, 1.0, 1.0}; } +vector float f7(void) { return (vector float){ 1.0, a, 1.0, a}; } +vector float f8(void) { return (vector float){ a, 1.0, a, 1.0}; } + +vector float fa(void) { return (vector float){ 1.0, 1.0, 0.0, 0.0}; } +vector float fb(void) { return (vector float){ 1.0, 0.0, 1.0, 0.0}; } +vector float fc(void) { return (vector float){ 0.0, 1.0, 0.0, 1.0}; } + +vector float fA(void) { return (vector float){ a, a, b, b}; } +vector float fB(void) { return (vector float){ a, b, a, b}; } +vector float fC(void) { return (vector float){ a, a, a, a}; } + +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/vecinit-6.c b/gcc/testsuite/gcc.target/i386/vecinit-6.c new file mode 100644 index 0000000..ba58f12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vecinit-6.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +#define vector __attribute__((vector_size(16))) + +int a, b; +vector int f1(void) { return (vector int){ 0, 0, a, a}; } +vector int f2(void) { return (vector int){ a, a, 0, 0}; } +vector int f3(void) { return (vector int){ 0, a, 0, a}; } +vector int f4(void) { return (vector int){ a, 0, a, 0}; } + +vector int f5(void) { return (vector int){ 1, 1, a, a}; } +vector int f6(void) { return (vector int){ a, a, 1, 1}; } +vector int f7(void) { return (vector int){ 1, a, 1, a}; } +vector int f8(void) { return (vector int){ a, 1, a, 1}; } + +vector int fa(void) { return (vector int){ 1, 1, 0, 0}; } +vector int fb(void) { return (vector int){ 1, 0, 1, 0}; } +vector int fc(void) { return (vector int){ 0, 1, 0, 1}; } + +vector int fA(void) { return (vector int){ a, a, b, b}; } +vector int fB(void) { return (vector int){ a, b, a, b}; } +vector int fC(void) { return (vector int){ a, a, a, a}; } + +/* { dg-final { scan-assembler-not "%mm" } } */ -- 2.7.4