From 784b407e8862223d868a6278fc6c5ca0a02e55b4 Mon Sep 17 00:00:00 2001 From: Boris Zanin Date: Mon, 11 Feb 2019 13:33:56 +0100 Subject: [PATCH] Add SPIR-V ids abuse tests Add tests: * dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.* * dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.* Components: vulkan VK-GL-CTS issue: 1583 Change-Id: I8cbb94616fc9175de36daf6804cde9b680284aa6 --- android/cts/master/vk-master.txt | 12 + .../spirv_assembly/vktSpvAsmInstructionTests.cpp | 283 ++++++++++++++++++++- .../mustpass/1.1.4/vk-default-no-waivers.txt | 12 + external/vulkancts/mustpass/1.1.4/vk-default.txt | 12 + 4 files changed, 318 insertions(+), 1 deletion(-) diff --git a/android/cts/master/vk-master.txt b/android/cts/master/vk-master.txt index 3ec7886..328537d 100755 --- a/android/cts/master/vk-master.txt +++ b/android/cts/master/vk-master.txt @@ -228075,6 +228075,8 @@ dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint64 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint32 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint16 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint8 +dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.sparse_ids +dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.lots_ids dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.flat dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.no_perspective dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.relaxedprecision @@ -240423,6 +240425,16 @@ dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimessc dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_tesse dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_geom dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_frag +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_vert +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_tessc +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_tesse +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_geom +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_frag +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_vert +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_tessc +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_tesse +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_geom +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_frag dEQP-VK.spirv_assembly.type.scalar.i8.negate_vert dEQP-VK.spirv_assembly.type.scalar.i8.negate_tessc dEQP-VK.spirv_assembly.type.scalar.i8.negate_tesse diff --git a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmInstructionTests.cpp b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmInstructionTests.cpp index 64da441..1d25d90 100644 --- a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmInstructionTests.cpp +++ b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmInstructionTests.cpp @@ -18046,6 +18046,286 @@ tcu::TestCaseGroup* createOpMemberNameAbuseTests (tcu::TestContext& testCtx) return abuseGroup.release(); } +vector getSparseIdsAbuseData (const deUint32 numDataPoints, const deUint32 seed) +{ + vector result; + de::Random rnd (seed); + + result.reserve(numDataPoints); + + for (deUint32 dataPointNdx = 0; dataPointNdx < numDataPoints; ++dataPointNdx) + result.push_back(rnd.getUint32()); + + return result; +} + +vector getSparseIdsAbuseResults (const vector& inData1, const vector& inData2) +{ + vector result; + + result.reserve(inData1.size()); + + for (size_t dataPointNdx = 0; dataPointNdx < inData1.size(); ++dataPointNdx) + result.push_back(inData1[dataPointNdx] + inData2[dataPointNdx]); + + return result; +} + +template +void createSparseIdsAbuseTest (tcu::TestContext& testCtx, de::MovePtr& testGroup) +{ + const deUint32 numDataPoints = 16; + const std::string testName ("sparse_ids"); + const deUint32 seed (deStringHash(testName.c_str())); + const vector inData1 (getSparseIdsAbuseData(numDataPoints, seed + 1)); + const vector inData2 (getSparseIdsAbuseData(numDataPoints, seed + 2)); + const vector outData (getSparseIdsAbuseResults(inData1, inData2)); + const StringTemplate preMain + ( + "%c_i32_ndp = OpConstant %i32 ${num_data_points}\n" + " %up_u32 = OpTypePointer Uniform %u32\n" + " %ra_u32 = OpTypeArray %u32 %c_i32_ndp\n" + " %SSBO32 = OpTypeStruct %ra_u32\n" + "%up_SSBO32 = OpTypePointer Uniform %SSBO32\n" + "%ssbo_src0 = OpVariable %up_SSBO32 Uniform\n" + "%ssbo_src1 = OpVariable %up_SSBO32 Uniform\n" + " %ssbo_dst = OpVariable %up_SSBO32 Uniform\n" + ); + const StringTemplate decoration + ( + "OpDecorate %ra_u32 ArrayStride 4\n" + "OpMemberDecorate %SSBO32 0 Offset 0\n" + "OpDecorate %SSBO32 BufferBlock\n" + "OpDecorate %ssbo_src0 DescriptorSet 0\n" + "OpDecorate %ssbo_src0 Binding 0\n" + "OpDecorate %ssbo_src1 DescriptorSet 0\n" + "OpDecorate %ssbo_src1 Binding 1\n" + "OpDecorate %ssbo_dst DescriptorSet 0\n" + "OpDecorate %ssbo_dst Binding 2\n" + ); + const StringTemplate testFun + ( + "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n" + " %param = OpFunctionParameter %v4f32\n" + + " %entry = OpLabel\n" + " %i = OpVariable %fp_i32 Function\n" + " OpStore %i %c_i32_0\n" + " OpBranch %loop\n" + + " %loop = OpLabel\n" + " %i_cmp = OpLoad %i32 %i\n" + " %lt = OpSLessThan %bool %i_cmp %c_i32_ndp\n" + " OpLoopMerge %merge %next None\n" + " OpBranchConditional %lt %write %merge\n" + + " %write = OpLabel\n" + " %ndx = OpLoad %i32 %i\n" + + " %127 = OpAccessChain %up_u32 %ssbo_src0 %c_i32_0 %ndx\n" + " %128 = OpLoad %u32 %127\n" + + // The test relies on SPIR-V compiler option SPV_TEXT_TO_BINARY_OPTION_PRESERVE_NUMERIC_IDS set in assembleSpirV() + " %4194000 = OpAccessChain %up_u32 %ssbo_src1 %c_i32_0 %ndx\n" + " %4194001 = OpLoad %u32 %4194000\n" + + " %2097151 = OpIAdd %u32 %128 %4194001\n" + " %2097152 = OpAccessChain %up_u32 %ssbo_dst %c_i32_0 %ndx\n" + " OpStore %2097152 %2097151\n" + " OpBranch %next\n" + + " %next = OpLabel\n" + " %i_cur = OpLoad %i32 %i\n" + " %i_new = OpIAdd %i32 %i_cur %c_i32_1\n" + " OpStore %i %i_new\n" + " OpBranch %loop\n" + + " %merge = OpLabel\n" + " OpReturnValue %param\n" + + " OpFunctionEnd\n" + ); + SpecResource specResource; + map specs; + VulkanFeatures features; + map fragments; + vector extensions; + + specs["num_data_points"] = de::toString(numDataPoints); + + fragments["decoration"] = decoration.specialize(specs); + fragments["pre_main"] = preMain.specialize(specs); + fragments["testfun"] = testFun.specialize(specs); + + specResource.inputs.push_back(Resource(BufferSp(new Uint32Buffer(inData1)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER)); + specResource.inputs.push_back(Resource(BufferSp(new Uint32Buffer(inData2)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER)); + specResource.outputs.push_back(Resource(BufferSp(new Uint32Buffer(outData)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER)); + + finalizeTestsCreation(specResource, fragments, testCtx, *testGroup.get(), testName, features, extensions, IVec3(1, 1, 1)); +} + +vector getLotsIdsAbuseData (const deUint32 numDataPoints, const deUint32 seed) +{ + vector result; + de::Random rnd (seed); + + result.reserve(numDataPoints); + + // Fixed value + result.push_back(1u); + + // Random values + for (deUint32 dataPointNdx = 1; dataPointNdx < numDataPoints; ++dataPointNdx) + result.push_back(rnd.getUint8()); + + return result; +} + +vector getLotsIdsAbuseResults (const vector& inData1, const vector& inData2, const deUint32 count) +{ + vector result; + + result.reserve(inData1.size()); + + for (size_t dataPointNdx = 0; dataPointNdx < inData1.size(); ++dataPointNdx) + result.push_back(inData1[dataPointNdx] + count * inData2[dataPointNdx]); + + return result; +} + +template +void createLotsIdsAbuseTest (tcu::TestContext& testCtx, de::MovePtr& testGroup) +{ + const deUint32 numDataPoints = 16; + const deUint32 firstNdx = 100u; + const deUint32 sequenceCount = 10000u; + const std::string testName ("lots_ids"); + const deUint32 seed (deStringHash(testName.c_str())); + const vector inData1 (getLotsIdsAbuseData(numDataPoints, seed + 1)); + const vector inData2 (getLotsIdsAbuseData(numDataPoints, seed + 2)); + const vector outData (getLotsIdsAbuseResults(inData1, inData2, sequenceCount)); + const StringTemplate preMain + ( + "%c_i32_ndp = OpConstant %i32 ${num_data_points}\n" + " %up_u32 = OpTypePointer Uniform %u32\n" + " %ra_u32 = OpTypeArray %u32 %c_i32_ndp\n" + " %SSBO32 = OpTypeStruct %ra_u32\n" + "%up_SSBO32 = OpTypePointer Uniform %SSBO32\n" + "%ssbo_src0 = OpVariable %up_SSBO32 Uniform\n" + "%ssbo_src1 = OpVariable %up_SSBO32 Uniform\n" + " %ssbo_dst = OpVariable %up_SSBO32 Uniform\n" + ); + const StringTemplate decoration + ( + "OpDecorate %ra_u32 ArrayStride 4\n" + "OpMemberDecorate %SSBO32 0 Offset 0\n" + "OpDecorate %SSBO32 BufferBlock\n" + "OpDecorate %ssbo_src0 DescriptorSet 0\n" + "OpDecorate %ssbo_src0 Binding 0\n" + "OpDecorate %ssbo_src1 DescriptorSet 0\n" + "OpDecorate %ssbo_src1 Binding 1\n" + "OpDecorate %ssbo_dst DescriptorSet 0\n" + "OpDecorate %ssbo_dst Binding 2\n" + ); + const StringTemplate testFun + ( + "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n" + " %param = OpFunctionParameter %v4f32\n" + + " %entry = OpLabel\n" + " %i = OpVariable %fp_i32 Function\n" + " OpStore %i %c_i32_0\n" + " OpBranch %loop\n" + + " %loop = OpLabel\n" + " %i_cmp = OpLoad %i32 %i\n" + " %lt = OpSLessThan %bool %i_cmp %c_i32_ndp\n" + " OpLoopMerge %merge %next None\n" + " OpBranchConditional %lt %write %merge\n" + + " %write = OpLabel\n" + " %ndx = OpLoad %i32 %i\n" + + " %90 = OpAccessChain %up_u32 %ssbo_src1 %c_i32_0 %ndx\n" + " %91 = OpLoad %u32 %90\n" + + " %98 = OpAccessChain %up_u32 %ssbo_src0 %c_i32_0 %ndx\n" + " %${zeroth_id} = OpLoad %u32 %98\n" + + "${seq}\n" + + // The test relies on SPIR-V compiler option SPV_TEXT_TO_BINARY_OPTION_PRESERVE_NUMERIC_IDS set in assembleSpirV() + " %dst = OpAccessChain %up_u32 %ssbo_dst %c_i32_0 %ndx\n" + " OpStore %dst %${last_id}\n" + " OpBranch %next\n" + + " %next = OpLabel\n" + " %i_cur = OpLoad %i32 %i\n" + " %i_new = OpIAdd %i32 %i_cur %c_i32_1\n" + " OpStore %i %i_new\n" + " OpBranch %loop\n" + + " %merge = OpLabel\n" + " OpReturnValue %param\n" + + " OpFunctionEnd\n" + ); + deUint32 lastId = firstNdx; + SpecResource specResource; + map specs; + VulkanFeatures features; + map fragments; + vector extensions; + std::string sequence; + + for (deUint32 sequenceNdx = 0; sequenceNdx < sequenceCount; ++sequenceNdx) + { + const deUint32 sequenceId = sequenceNdx + firstNdx; + const std::string sequenceIdStr = de::toString(sequenceId); + + sequence += "%" + sequenceIdStr + " = OpIAdd %u32 %91 %" + de::toString(sequenceId - 1) + "\n"; + lastId = sequenceId; + + if (sequenceNdx == 0) + sequence.reserve((10 + sequence.length()) * sequenceCount); + } + + specs["num_data_points"] = de::toString(numDataPoints); + specs["zeroth_id"] = de::toString(firstNdx - 1); + specs["last_id"] = de::toString(lastId); + specs["seq"] = sequence; + + fragments["decoration"] = decoration.specialize(specs); + fragments["pre_main"] = preMain.specialize(specs); + fragments["testfun"] = testFun.specialize(specs); + + specResource.inputs.push_back(Resource(BufferSp(new Uint32Buffer(inData1)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER)); + specResource.inputs.push_back(Resource(BufferSp(new Uint32Buffer(inData2)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER)); + specResource.outputs.push_back(Resource(BufferSp(new Uint32Buffer(outData)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER)); + + finalizeTestsCreation(specResource, fragments, testCtx, *testGroup.get(), testName, features, extensions, IVec3(1, 1, 1)); +} + +tcu::TestCaseGroup* createSpirvIdsAbuseTests (tcu::TestContext& testCtx) +{ + de::MovePtr testGroup (new tcu::TestCaseGroup(testCtx, "spirv_ids_abuse", "SPIR-V abuse tests")); + + createSparseIdsAbuseTest(testCtx, testGroup); + createLotsIdsAbuseTest(testCtx, testGroup); + + return testGroup.release(); +} + +tcu::TestCaseGroup* createSpirvIdsAbuseGroup (tcu::TestContext& testCtx) +{ + de::MovePtr testGroup (new tcu::TestCaseGroup(testCtx, "spirv_ids_abuse", "SPIR-V abuse tests")); + + createSparseIdsAbuseTest(testCtx, testGroup); + createLotsIdsAbuseTest(testCtx, testGroup); + + return testGroup.release(); +} + tcu::TestCaseGroup* createInstructionTests (tcu::TestContext& testCtx) { const bool testComputePipeline = true; @@ -18128,6 +18408,7 @@ tcu::TestCaseGroup* createInstructionTests (tcu::TestContext& testCtx) computeTests->addChild(createFloat16Group(testCtx)); computeTests->addChild(createBoolGroup(testCtx)); computeTests->addChild(createWorkgroupMemoryComputeGroup(testCtx)); + computeTests->addChild(createSpirvIdsAbuseGroup(testCtx)); graphicsTests->addChild(createCrossStageInterfaceTests(testCtx)); graphicsTests->addChild(createSpivVersionCheckTests(testCtx, !testComputePipeline)); @@ -18187,8 +18468,8 @@ tcu::TestCaseGroup* createInstructionTests (tcu::TestContext& testCtx) graphicsTests->addChild(createConvertGraphicsTests(testCtx, "OpConvertFToU", "convertftou")); graphicsTests->addChild(createPointerParameterGraphicsGroup(testCtx)); graphicsTests->addChild(createVaryingNameGraphicsGroup(testCtx)); - graphicsTests->addChild(createFloat16Tests(testCtx)); + graphicsTests->addChild(createSpirvIdsAbuseTests(testCtx)); instructionTests->addChild(computeTests.release()); instructionTests->addChild(graphicsTests.release()); diff --git a/external/vulkancts/mustpass/1.1.4/vk-default-no-waivers.txt b/external/vulkancts/mustpass/1.1.4/vk-default-no-waivers.txt index f8851d6..1db0164 100644 --- a/external/vulkancts/mustpass/1.1.4/vk-default-no-waivers.txt +++ b/external/vulkancts/mustpass/1.1.4/vk-default-no-waivers.txt @@ -228089,6 +228089,8 @@ dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint64 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint32 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint16 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint8 +dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.sparse_ids +dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.lots_ids dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.flat dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.no_perspective dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.relaxedprecision @@ -240447,6 +240449,16 @@ dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimessc dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_tesse dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_geom dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_frag +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_vert +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_tessc +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_tesse +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_geom +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_frag +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_vert +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_tessc +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_tesse +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_geom +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_frag dEQP-VK.spirv_assembly.type.scalar.i8.negate_vert dEQP-VK.spirv_assembly.type.scalar.i8.negate_tessc dEQP-VK.spirv_assembly.type.scalar.i8.negate_tesse diff --git a/external/vulkancts/mustpass/1.1.4/vk-default.txt b/external/vulkancts/mustpass/1.1.4/vk-default.txt index 42acc41..3ed8025 100644 --- a/external/vulkancts/mustpass/1.1.4/vk-default.txt +++ b/external/vulkancts/mustpass/1.1.4/vk-default.txt @@ -228089,6 +228089,8 @@ dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint64 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint32 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint16 dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint8 +dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.sparse_ids +dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.lots_ids dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.flat dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.no_perspective dEQP-VK.spirv_assembly.instruction.graphics.cross_stage.basic_type.relaxedprecision @@ -240447,6 +240449,16 @@ dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimessc dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_tesse dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_geom dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.opvectortimesscalar_frag +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_vert +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_tessc +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_tesse +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_geom +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.sparse_ids_frag +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_vert +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_tessc +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_tesse +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_geom +dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_frag dEQP-VK.spirv_assembly.type.scalar.i8.negate_vert dEQP-VK.spirv_assembly.type.scalar.i8.negate_tessc dEQP-VK.spirv_assembly.type.scalar.i8.negate_tesse -- 2.7.4