From 782ba8d3ae55af392da8ca829f3a185c10bbecfc Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Wed, 5 Aug 2020 18:07:06 +0300 Subject: [PATCH] st/mesa: Treat vertex outputs absent in outputMapping as zero in mesa_to_tgsi MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit After updating vertex outputs being written based on optimized NIR, they may go out of sync with outputs in mesa IR. Which is translated to TGSI and used together with NIR if draw doesn't have llvm. It's much easier to treat such outputs as zero because there is no pass to entirely get rid of them. Similar to eeab9c93db84e5759145891e8fdde66a5cdcf917 but now for outputs. Fixes: d684fb37bfbc47d098158cb03c0672119a4469fe Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3365 Signed-off-by: Danylo Piliaiev Reviewed-by: Marek Olšák Part-of: --- src/mesa/state_tracker/st_mesa_to_tgsi.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c index 6fe8f85..dca9acb 100644 --- a/src/mesa/state_tracker/st_mesa_to_tgsi.c +++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c @@ -97,9 +97,12 @@ dst_register(struct st_translate *t, gl_register_file file, GLuint index) else assert(index < VARYING_SLOT_MAX); - assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs)); - - return t->outputs[t->outputMapping[index]]; + if (t->outputMapping[index] < ARRAY_SIZE(t->outputs)) + return t->outputs[t->outputMapping[index]]; + else { + assert(t->procType == PIPE_SHADER_VERTEX); + return ureg_dst(ureg_DECL_constant(t->ureg, 0)); + } case PROGRAM_ADDRESS: return t->address[index]; @@ -149,8 +152,12 @@ src_register(struct st_translate *t, } case PROGRAM_OUTPUT: - assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs)); - return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */ + if (t->outputMapping[index] < ARRAY_SIZE(t->outputs)) + return ureg_src(t->outputs[t->outputMapping[index]]); + else { + assert(t->procType == PIPE_SHADER_VERTEX); + return ureg_DECL_constant(t->ureg, 0); + } case PROGRAM_ADDRESS: return ureg_src(t->address[index]); -- 2.7.4