From 7820518d55f9c40cd55adbe7185743e1bd2c936d Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Fri, 26 Feb 2021 09:52:03 -0800 Subject: [PATCH] [InstCombine][NFC]Add a test for logical reductions. --- .../InstCombine/vector-logical-reductions.ll | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/vector-logical-reductions.ll diff --git a/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll b/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll new file mode 100644 index 0000000..f90a7c2 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +define float @reduction_logical_or(<4 x float> %x) { +; CHECK-LABEL: @reduction_logical_or( +; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <4 x float> [[X:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP1]]) +; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], float -1.000000e+00, float 1.000000e+00 +; CHECK-NEXT: ret float [[R]] +; + %1 = fcmp ogt <4 x float> %x, + %2 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %1) + %r = select i1 %2, float -1.000000e+00, float 1.000000e+00 + ret float %r +} + +define float @reduction_logical_and(<4 x float> %x) { +; CHECK-LABEL: @reduction_logical_and( +; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <4 x float> [[X:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP1]]) +; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], float -1.000000e+00, float 1.000000e+00 +; CHECK-NEXT: ret float [[R]] +; + %1 = fcmp ogt <4 x float> %x, + %2 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %1) + %r = select i1 %2, float -1.000000e+00, float 1.000000e+00 + ret float %r +} + +declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>) +declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>) -- 2.7.4