From 781dedba3022c90bd64bd580a5d146d1eea794f4 Mon Sep 17 00:00:00 2001 From: Monk Chiang Date: Wed, 11 Jan 2023 20:59:40 -0800 Subject: [PATCH] [RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions The Reduction instruction destination register LMUL is 1. But the source register(vs2) has different LMUL(MF8 to M8). It's beneficial to know how many registers are working on reduction instructions. This patch creates separate SchedWrite for each relevant LMUL that from VS2. Reviewed By: michaelmaitland Differential Revision: https://reviews.llvm.org/D141565 --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 18 ++++++---- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 25 +++++++++++--- llvm/lib/Target/RISCV/RISCVScheduleV.td | 45 ++++++++++++++++++------- 3 files changed, 65 insertions(+), 23 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index eec6973..d1d436b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -725,32 +725,38 @@ multiclass VNCVTF_FV_VS2 funct6, bits<5> vs1> { multiclass VRED_MV_V funct6> { def _VS : VALUVV, - Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV0, ReadVMask]>; + Sched<[WriteVIRedV_From_UpperBound, ReadVIRedV, ReadVIRedV0, + ReadVMask]>; } multiclass VWRED_IV_V funct6> { def _VS : VALUVV, - Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV0, ReadVMask]>; + Sched<[WriteVIWRedV_From_UpperBound, ReadVIWRedV, ReadVIWRedV0, + ReadVMask]>; } multiclass VRED_FV_V funct6> { def _VS : VALUVV, - Sched<[WriteVFRedV, ReadVFRedV, ReadVFRedV0, ReadVMask]>; + Sched<[WriteVFRedV_From_UpperBound, ReadVFRedV, ReadVFRedV0, + ReadVMask]>; } multiclass VREDO_FV_V funct6> { def _VS : VALUVV, - Sched<[WriteVFRedOV, ReadVFRedOV, ReadVFRedOV0, ReadVMask]>; + Sched<[WriteVFRedOV_From_UpperBound, ReadVFRedOV, ReadVFRedOV0, + ReadVMask]>; } multiclass VWRED_FV_V funct6> { def _VS : VALUVV, - Sched<[WriteVFWRedV, ReadVFWRedV, ReadVFWRedV0, ReadVMask]>; + Sched<[WriteVFWRedV_From_UpperBound, ReadVFWRedV, ReadVFWRedV0, + ReadVMask]>; } multiclass VWREDO_FV_V funct6> { def _VS : VALUVV, - Sched<[WriteVFWRedOV, ReadVFWRedOV, ReadVFWRedOV0, ReadVMask]>; + Sched<[WriteVFWRedOV_From_UpperBound, ReadVFWRedOV, ReadVFWRedOV0, + ReadVMask]>; } multiclass VMALU_MV_Mask funct6, string vm = "v"> { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 3f69b5e..04a6890 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3297,36 +3297,51 @@ multiclass VPseudoVCMPM_VX_VI { multiclass VPseudoVRED_VS { foreach m = MxList in { + defvar mx = m.MX; + defvar WriteVIRedV_From_MX = !cast("WriteVIRedV_From_" # mx); defm _VS : VPseudoTernary, - Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV, ReadVIRedV, ReadVMask]>; + Sched<[WriteVIRedV_From_MX, ReadVIRedV, ReadVIRedV, ReadVIRedV, + ReadVMask]>; } } multiclass VPseudoVWRED_VS { foreach m = MxList in { + defvar mx = m.MX; + defvar WriteVIWRedV_From_MX = !cast("WriteVIWRedV_From_" # mx); defm _VS : VPseudoTernary, - Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVMask]>; + Sched<[WriteVIWRedV_From_MX, ReadVIWRedV, ReadVIWRedV, + ReadVIWRedV, ReadVMask]>; } } multiclass VPseudoVFRED_VS { foreach m = MxListF in { + defvar mx = m.MX; + defvar WriteVFRedV_From_MX = !cast("WriteVFRedV_From_" # mx); defm _VS : VPseudoTernary, - Sched<[WriteVFRedV, ReadVFRedV, ReadVFRedV, ReadVFRedV, ReadVMask]>; + Sched<[WriteVFRedV_From_MX, ReadVFRedV, ReadVFRedV, ReadVFRedV, + ReadVMask]>; } } multiclass VPseudoVFREDO_VS { foreach m = MxListF in { + defvar mx = m.MX; + defvar WriteVFRedOV_From_MX = !cast("WriteVFRedOV_From_" # mx); defm _VS : VPseudoTernary, - Sched<[WriteVFRedOV, ReadVFRedOV, ReadVFRedOV, ReadVFRedOV, ReadVMask]>; + Sched<[WriteVFRedOV_From_MX, ReadVFRedOV, ReadVFRedOV, + ReadVFRedOV, ReadVMask]>; } } multiclass VPseudoVFWRED_VS { foreach m = MxListF in { + defvar mx = m.MX; + defvar WriteVFWRedV_From_MX = !cast("WriteVFWRedV_From_" # mx); defm _VS : VPseudoTernary, - Sched<[WriteVFWRedV, ReadVFWRedV, ReadVFWRedV, ReadVFWRedV, ReadVMask]>; + Sched<[WriteVFWRedV_From_MX, ReadVFWRedV, ReadVFWRedV, + ReadVFWRedV, ReadVMask]>; } } diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td index 62054b0..c7d6370 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -14,6 +14,8 @@ defvar SchedMxList = ["UpperBound", "M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"] // Used for widening and narrowing instructions as it doesn't contain M8. defvar SchedMxListW = ["UpperBound", "MF8", "MF4", "MF2", "M1", "M2", "M4"]; defvar SchedMxListFW = ["UpperBound", "MF4", "MF2", "M1", "M2", "M4"]; +// Used for widening floating-point Reduction as it doesn't contain MF8. +defvar SchedMxListFWRed = ["UpperBound", "MF4", "MF2", "M1", "M2", "M4", "M8"]; // Creates SchedWrite for each (name, LMUL) pair for LMUL in SchedMxList multiclass LMULSchedWrites { @@ -36,6 +38,13 @@ multiclass LMULSchedWritesFW { } } +// Creates SchedWrite for each (name, LMUL) pair for LMUL in SchedMxListFWRed +multiclass LMULSchedWritesFWRed { + foreach mx = SchedMxListFWRed in { + def name # "_" # mx : SchedWrite; + } +} + // Creates SchedRead for each (name, LMUL) pair for LMUL in SchedMxList multiclass LMULSchedReads { foreach mx = SchedMxList in { @@ -81,6 +90,14 @@ multiclass LMULWriteResFW resources> { } } +// Creates WriteRes for each (name, LMUL, resources) tuple for LMUL +// in SchedMxListFWRed +multiclass LMULWriteResFWRed resources> { + foreach mx = SchedMxListFWRed in { + def : WriteRes(name # "_" # mx), resources>; + } +} + // Creates ReadAdvance for each (name, LMUL, val) tuple for LMUL // in SchedMxList multiclass LMULReadAdvance writes = []> { @@ -297,16 +314,20 @@ defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">; defm "" : LMULSchedWritesFW<"WriteVFNCvtFToFV">; // 14. Vector Reduction Operations +// The latency of reduction is determined by the size of the read resource. +// The LMUL range of read resource(VS2) for reduction operantion is between +// MF8 and M8. Use the _From suffix to indicate the number of the +// LMUL from VS2. // 14.1. Vector Single-Width Integer Reduction Instructions -def WriteVIRedV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVIRedV_From">; // 14.2. Vector Widening Integer Reduction Instructions -def WriteVIWRedV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVIWRedV_From">; // 14.3. Vector Single-Width Floating-Point Reduction Instructions -def WriteVFRedV : SchedWrite; -def WriteVFRedOV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVFRedV_From">; +defm "" : LMULSchedWrites<"WriteVFRedOV_From">; // 14.4. Vector Widening Floating-Point Reduction Instructions -def WriteVFWRedV : SchedWrite; -def WriteVFWRedOV : SchedWrite; +defm "" : LMULSchedWritesFWRed<"WriteVFWRedV_From">; +defm "" : LMULSchedWritesFWRed<"WriteVFWRedOV_From">; // 15. Vector Mask Instructions // 15.1. Vector Mask-Register Logical Instructions @@ -727,12 +748,12 @@ defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>; defm "" : LMULWriteResFW<"WriteVFNCvtFToFV", []>; // 14. Vector Reduction Operations -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; +defm "" : LMULWriteRes<"WriteVIRedV_From", []>; +defm "" : LMULWriteRes<"WriteVIWRedV_From", []>; +defm "" : LMULWriteRes<"WriteVFRedV_From", []>; +defm "" : LMULWriteRes<"WriteVFRedOV_From", []>; +defm "" : LMULWriteResFWRed<"WriteVFWRedV_From", []>; +defm "" : LMULWriteResFWRed<"WriteVFWRedOV_From", []>; // 15. Vector Mask Instructions defm "" : LMULWriteRes<"WriteVMALUV", []>; -- 2.7.4