From 77df976a1219c0c6fd102358c15e71747aab4443 Mon Sep 17 00:00:00 2001 From: Ricky Zhou Date: Sun, 14 May 2023 16:53:04 +0100 Subject: [PATCH] [LV] Add test case for #51677. --- llvm/test/Transforms/LoopVectorize/pr52335.ll | 150 ++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/pr52335.ll diff --git a/llvm/test/Transforms/LoopVectorize/pr52335.ll b/llvm/test/Transforms/LoopVectorize/pr52335.ll new file mode 100644 index 0000000..feec2d2 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/pr52335.ll @@ -0,0 +1,150 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s + +; The vectorizer should refuse to fold the tail by masking because +; %conv is used outside of the loop. +define i32 @test(ptr nocapture %arr, i64 %n) { +Test for this by checking that +; CHECK-LABEL: define i32 @test +; CHECK-SAME: (ptr nocapture [[ARR:%.*]], i64 [[N:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[N]], 1 +; CHECK-NEXT: br i1 [[CMP1]], label [[PREHEADER:%.*]], label [[DONE:%.*]] +; CHECK: preheader: +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1 +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], -2 +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i8 +; CHECK-NEXT: [[TMP3:%.*]] = add i8 1, [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP1]], 255 +; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP1]] to i8 +; CHECK-NEXT: [[TMP8:%.*]] = add i8 2, [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i8 [[TMP8]], 2 +; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP1]], 255 +; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP6]], [[TMP11]] +; CHECK-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 3 +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; CHECK-NEXT: [[IND_END:%.*]] = add i64 1, [[N_VEC]] +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i8 +; CHECK-NEXT: [[IND_END1:%.*]] = add i8 1, [[DOTCAST]] +; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[TMP0]], 1 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE10:%.*]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE10]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]] +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 1 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 2 +; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[OFFSET_IDX]], 3 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT3]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT4]], +; CHECK-NEXT: [[TMP17:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP18:%.*]] = add nsw <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP17]], i32 0 +; CHECK-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; CHECK: pred.store.if: +; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i64> [[TMP18]], i32 0 +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP20]] +; CHECK-NEXT: store i32 65, ptr [[TMP21]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] +; CHECK: pred.store.continue: +; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i1> [[TMP17]], i32 1 +; CHECK-NEXT: br i1 [[TMP22]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]] +; CHECK: pred.store.if5: +; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i64> [[TMP18]], i32 1 +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP23]] +; CHECK-NEXT: store i32 65, ptr [[TMP24]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]] +; CHECK: pred.store.continue6: +; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i1> [[TMP17]], i32 2 +; CHECK-NEXT: br i1 [[TMP25]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]] +; CHECK: pred.store.if7: +; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i64> [[TMP18]], i32 2 +; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP26]] +; CHECK-NEXT: store i32 65, ptr [[TMP27]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]] +; CHECK: pred.store.continue8: +; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i1> [[TMP17]], i32 3 +; CHECK-NEXT: br i1 [[TMP28]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10]] +; CHECK: pred.store.if9: +; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i64> [[TMP18]], i32 3 +; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP29]] +; CHECK-NEXT: store i32 65, ptr [[TMP30]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]] +; CHECK: pred.store.continue10: +; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP31:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP31]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMO:%.*]] = sub i64 [[N_VEC]], 1 +; CHECK-NEXT: [[IND_ESCAPE:%.*]] = add i64 1, [[CMO]] +; CHECK-NEXT: br i1 true, label [[LOAD_VAL:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1, [[PREHEADER]] ], [ 1, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i8 [ [[IND_END1]], [[MIDDLE_BLOCK]] ], [ 1, [[PREHEADER]] ], [ 1, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[CONV:%.*]] = phi i64 [ [[CONV2:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[I:%.*]] = phi i8 [ [[INC:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[SUB:%.*]] = add nsw i64 [[CONV]], -1 +; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[SUB]] +; CHECK-NEXT: store i32 65, ptr [[PTR]], align 4 +; CHECK-NEXT: [[INC]] = add i8 [[I]], 1 +; CHECK-NEXT: [[CONV2]] = zext i8 [[INC]] to i64 +; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[CONV2]], [[N]] +; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[LOAD_VAL]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: load_val: +; CHECK-NEXT: [[FINAL:%.*]] = phi i64 [ [[CONV]], [[LOOP]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[FINAL]] +; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[PTR2]], align 4 +; CHECK-NEXT: br label [[DONE]] +; CHECK: done: +; CHECK-NEXT: [[VALUE:%.*]] = phi i32 [ [[VAL]], [[LOAD_VAL]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i32 [[VALUE]] +; +entry: + %cmp1 = icmp ugt i64 %n, 1 + br i1 %cmp1, label %preheader, label %done + +preheader: + br label %loop + +loop: + %conv = phi i64 [ %conv2, %loop ], [ 1, %preheader ] + %i = phi i8 [ %inc, %loop ], [ 1, %preheader ] + %sub = add nsw i64 %conv, -1 + %ptr = getelementptr inbounds i32, ptr %arr, i64 %sub + store i32 65, ptr %ptr, align 4 + %inc = add i8 %i, 1 + %conv2 = zext i8 %inc to i64 + %cmp2 = icmp ult i64 %conv2, %n + br i1 %cmp2, label %loop, label %load_val, !llvm.loop !0 + +load_val: + %final = phi i64 [ %conv, %loop ] + %ptr2 = getelementptr inbounds i32, ptr %arr, i64 %final + %val = load i32, ptr %ptr2, align 4 + br label %done + +done: + %value = phi i32 [ %val, %load_val ], [ 0, %entry ] + ret i32 %value + +} + +!0 = distinct !{!0, !1, !2, !3} +!1 = !{!"llvm.loop.unroll.disable"} +!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true} +!3 = !{!"llvm.loop.vectorize.enable", i1 true} -- 2.7.4