From 77482120dae780444cff02fbe5ce4cdd8a71873a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 19 Mar 2019 18:55:46 +0000 Subject: [PATCH] Fix for ABS legalization on PPC buildbot. llvm-svn: 356498 --- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index e25294cf1741..f14b2e4cfabf 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -2665,6 +2665,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { // any other unary ops. LLVM_FALLTHROUGH; + case ISD::ABS: case ISD::BITREVERSE: case ISD::BSWAP: case ISD::CTLZ: diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 2b1003663b6e..aa3fc7c315bb 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -551,8 +551,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // add/sub are legal for all supported vector VT's. setOperationAction(ISD::ADD, VT, Legal); setOperationAction(ISD::SUB, VT, Legal); - if (VT.getSizeInBits() == 128) - setOperationAction(ISD::ABS, VT, Custom); // Vector instructions introduced in P8 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { @@ -638,6 +636,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, } } + for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8}) + setOperationAction(ISD::ABS, VT, Custom); + // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle // with merges, splats, etc. setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); -- 2.34.1