From 7747a142abcaa6406d509846ccd4bdcc17c7fd2a Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 2 Feb 2023 13:38:37 +0000 Subject: [PATCH] [AMDGPU] GFX11: accept global_atomic_csub as an alias GFX11 renamed this instruction to global_atomic_csub_u32 but should accept the old name as an alias, for consistency with the other global atomics and with buffer_atomic_csub. Differential Revision: https://reviews.llvm.org/D143176 --- llvm/lib/Target/AMDGPU/FLATInstructions.td | 15 ++++++++++----- llvm/test/MC/AMDGPU/gfx11_asm_flat.s | 30 ++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index dff3091..d5c44f9 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -2171,12 +2171,16 @@ class FLAT_Real_gfx11 op, FLAT_Pseudo ps, string opName = ps.Mnemonic> let Inst{55} = ps.sve; } -multiclass FLAT_Real_Base_gfx11 op, string ps, string opName, int renamed = false> { +multiclass FLAT_Aliases_gfx11 { + if renamed then + def _renamed_gfx11 : MnemonicAlias(ps).Mnemonic, opName>, Requires<[isGFX11Plus]>; +} + +multiclass FLAT_Real_Base_gfx11 op, string ps, string opName, int renamed = false> : + FLAT_Aliases_gfx11 { def _gfx11 : FLAT_Real_gfx11(ps), opName> { let Inst{54-48} = !cast(SGPR_NULL_gfx11plus.HWEncoding); } - if renamed then - def _renamed_gfx11 : MnemonicAlias(ps).Mnemonic, opName>, Requires<[isGFX11Plus]>; } multiclass FLAT_Real_RTN_gfx11 op, string ps, string opName> { @@ -2219,7 +2223,8 @@ multiclass FLAT_Real_GlblAtomics_gfx11 op, string ps, string opName, int FLAT_Real_RTN_gfx11, FLAT_Real_SADDR_RTN_gfx11; -multiclass FLAT_Real_GlblAtomics_RTN_gfx11 op, string ps, string opName> : +multiclass FLAT_Real_GlblAtomics_RTN_gfx11 op, string ps, string opName, int renamed = false> : + FLAT_Aliases_gfx11, FLAT_Real_RTN_gfx11, FLAT_Real_SADDR_RTN_gfx11; @@ -2312,7 +2317,7 @@ defm GLOBAL_ATOMIC_SWAP_B32 : FLAT_Real_GlblAtomics_gfx11<0x033, "GLOBAL_ATO defm GLOBAL_ATOMIC_CMPSWAP_B32 : FLAT_Real_GlblAtomics_gfx11<0x034, "GLOBAL_ATOMIC_CMPSWAP", "global_atomic_cmpswap_b32", true>; defm GLOBAL_ATOMIC_ADD_U32 : FLAT_Real_GlblAtomics_gfx11<0x035, "GLOBAL_ATOMIC_ADD", "global_atomic_add_u32", true>; defm GLOBAL_ATOMIC_SUB_U32 : FLAT_Real_GlblAtomics_gfx11<0x036, "GLOBAL_ATOMIC_SUB", "global_atomic_sub_u32", true>; -defm GLOBAL_ATOMIC_CSUB_U32 : FLAT_Real_GlblAtomics_RTN_gfx11<0x037, "GLOBAL_ATOMIC_CSUB", "global_atomic_csub_u32">; +defm GLOBAL_ATOMIC_CSUB_U32 : FLAT_Real_GlblAtomics_RTN_gfx11<0x037, "GLOBAL_ATOMIC_CSUB", "global_atomic_csub_u32", true>; defm GLOBAL_ATOMIC_MIN_I32 : FLAT_Real_GlblAtomics_gfx11<0x038, "GLOBAL_ATOMIC_SMIN", "global_atomic_min_i32", true>; defm GLOBAL_ATOMIC_MIN_U32 : FLAT_Real_GlblAtomics_gfx11<0x039, "GLOBAL_ATOMIC_UMIN", "global_atomic_min_u32", true>; defm GLOBAL_ATOMIC_MAX_I32 : FLAT_Real_GlblAtomics_gfx11<0x03a, "GLOBAL_ATOMIC_SMAX", "global_atomic_max_i32", true>; diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_flat.s b/llvm/test/MC/AMDGPU/gfx11_asm_flat.s index f940729..b0c212d 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_flat.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_flat.s @@ -1533,6 +1533,36 @@ global_atomic_cmpswap_x2 v[5:6], v255, v[2:5], vcc offset:4095 glc global_atomic_cmpswap_x2 v[254:255], v255, v[252:255], ttmp[14:15] offset:-4096 glc slc dlc // GFX11: [0x00,0xf0,0x0a,0xdd,0xff,0xfc,0x7a,0xfe] +global_atomic_csub v5, v[1:2], v2, off glc +// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x7c,0x05] + +global_atomic_csub v5, v[254:255], v2, off glc +// GFX11: [0x00,0x40,0xde,0xdc,0xfe,0x02,0x7c,0x05] + +global_atomic_csub v5, v1, v2, s[6:7] glc +// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x06,0x05] + +global_atomic_csub v5, v1, v2, s[104:105] glc +// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x68,0x05] + +global_atomic_csub v5, v1, v2, vcc glc +// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x6a,0x05] + +global_atomic_csub v5, v1, v2, ttmp[14:15] glc +// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x7a,0x05] + +global_atomic_csub v5, v255, v2, s[6:7] offset:-1 glc +// GFX11: [0xff,0x5f,0xde,0xdc,0xff,0x02,0x06,0x05] + +global_atomic_csub v5, v255, v2, s[104:105] offset:0 glc +// GFX11: [0x00,0x40,0xde,0xdc,0xff,0x02,0x68,0x05] + +global_atomic_csub v5, v255, v2, vcc offset:4095 glc +// GFX11: [0xff,0x4f,0xde,0xdc,0xff,0x02,0x6a,0x05] + +global_atomic_csub v255, v255, v255, ttmp[14:15] offset:-4096 glc slc dlc +// GFX11: [0x00,0xf0,0xde,0xdc,0xff,0xff,0x7a,0xff] + global_atomic_csub_u32 v5, v[1:2], v2, off glc // GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x7c,0x05] -- 2.7.4