From 773c7cbcbc987f145ecf0e4ae6739b0dbd6966bb Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 30 Jul 2021 18:08:16 +0100 Subject: [PATCH] radv,aco: implement 64-bit inline push constants MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit fossil-db (Sienna Cichlid): Totals from 21 (0.02% of 134621) affected shaders: CodeSize: 1932 -> 1560 (-19.25%) Instrs: 357 -> 303 (-15.13%) Latency: 6576 -> 5883 (-10.54%) InvThroughput: 26304 -> 23532 (-10.54%) SClause: 42 -> 24 (-42.86%) Copies: 90 -> 105 (+16.67%); split: -10.00%, +26.67% PreSGPRs: 144 -> 201 (+39.58%) Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 5 ++++- src/amd/llvm/ac_nir_to_llvm.c | 10 ++++++++-- src/amd/vulkan/radv_shader_info.c | 2 +- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index e29817b..7caba87 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5500,7 +5500,10 @@ visit_load_push_constant(isel_context* ctx, nir_intrinsic_instr* instr) unsigned count = instr->dest.ssa.num_components; nir_const_value* index_cv = nir_src_as_const_value(instr->src[0]); - if (index_cv && instr->dest.ssa.bit_size == 32) { + if (instr->dest.ssa.bit_size == 64) + count *= 2; + + if (index_cv && instr->dest.ssa.bit_size >= 32) { unsigned start = (offset + index_cv->u32) / 4u; uint64_t mask = BITFIELD64_MASK(count) << start; if ((ctx->args->ac.inline_push_const_mask | mask) == ctx->args->ac.inline_push_const_mask && diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 1b3caab..6928803 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -1655,10 +1655,13 @@ static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx, nir_int /* Load constant values from user SGPRS when possible, otherwise * fallback to the default path that loads directly from memory. */ - if (LLVMIsConstant(src0) && instr->dest.ssa.bit_size == 32) { + if (LLVMIsConstant(src0) && instr->dest.ssa.bit_size >= 32) { unsigned count = instr->dest.ssa.num_components; unsigned offset = index; + if (instr->dest.ssa.bit_size == 64) + count *= 2; + offset += LLVMConstIntGetZExtValue(src0); offset /= 4; @@ -1670,7 +1673,10 @@ static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx, nir_int util_bitcount64(ctx->args->inline_push_const_mask & BITFIELD64_MASK(offset)); for (unsigned i = 0; i < count; i++) push_constants[i] = ac_get_arg(&ctx->ac, ctx->args->inline_push_consts[arg_index++]); - return ac_build_gather_values(&ctx->ac, push_constants, count); + LLVMValueRef res = ac_build_gather_values(&ctx->ac, push_constants, count); + return instr->dest.ssa.bit_size == 64 + ? LLVMBuildBitCast(ctx->ac.builder, res, get_def_type(ctx, &instr->dest.ssa), "") + : res; } } diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index baef1dc..f374ad2 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -98,7 +98,7 @@ gather_push_constant_info(const nir_shader *nir, const nir_intrinsic_instr *inst { info->loads_push_constants = true; - if (nir_src_is_const(instr->src[0]) && instr->dest.ssa.bit_size == 32) { + if (nir_src_is_const(instr->src[0]) && instr->dest.ssa.bit_size >= 32) { uint32_t start = (nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0])) / 4u; uint32_t size = instr->num_components * (instr->dest.ssa.bit_size / 32u); -- 2.7.4