From 76f33cbf25b01ff0a13a36e85a5c7df48d4adc98 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 22 Aug 2022 15:00:50 +0200 Subject: [PATCH] radv: remove redundant assignment of tcs.tcs_vertices_out MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit It's already assigned from radv_nir_shader_info_pass() and it's only used to configure the VGT_TF_PARAM register. Otherwise, we read it from NIR shader info during compilation. Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_pipeline.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 40ec9cb..750866b 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3614,7 +3614,6 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages, stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches = num_patches; stages[MESA_SHADER_GEOMETRY].info.num_tess_patches = num_patches; stages[MESA_SHADER_VERTEX].info.num_tess_patches = num_patches; - stages[MESA_SHADER_TESS_CTRL].info.tcs.tcs_vertices_out = tess_out_patch_size; stages[MESA_SHADER_VERTEX].info.tcs.tcs_vertices_out = tess_out_patch_size; if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) { -- 2.7.4