From 76a27f3a32f619d386fb8efa1563ba21b76e9170 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 27 Jun 2023 18:06:29 +0100 Subject: [PATCH] [X86] Add getBitSelect helper function to create OR(AND(LHS,MASK),AND(RHS,~MASK)) bit select patterns. NFC. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f981057..ead2d07 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7162,6 +7162,14 @@ static SDValue getEXTEND_VECTOR_INREG(unsigned Opcode, const SDLoc &DL, EVT VT, return DAG.getNode(Opcode, DL, VT, In); } +// Create OR(AND(LHS,MASK),AND(RHS,~MASK)) bit select pattern +static SDValue getBitSelect(const SDLoc &DL, MVT VT, SDValue LHS, SDValue RHS, + SDValue Mask, SelectionDAG &DAG) { + LHS = DAG.getNode(ISD::AND, DL, VT, LHS, Mask); + RHS = DAG.getNode(X86ISD::ANDNP, DL, VT, Mask, RHS); + return DAG.getNode(ISD::OR, DL, VT, LHS, RHS); +} + // Match (xor X, -1) -> X. // Match extract_subvector(xor X, -1) -> extract_subvector(X). // Match concat_vectors(xor X, -1, xor Y, -1) -> concat_vectors(X, Y). @@ -13059,9 +13067,7 @@ static SDValue lowerShuffleAsBitBlend(const SDLoc &DL, MVT VT, SDValue V1, } SDValue V1Mask = DAG.getBuildVector(VT, DL, MaskOps); - V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask); - V2 = DAG.getNode(X86ISD::ANDNP, DL, VT, V1Mask, V2); - return DAG.getNode(ISD::OR, DL, VT, V1, V2); + return getBitSelect(DL, VT, V1, V2, V1Mask, DAG); } static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask, -- 2.7.4