From 76454afd2d9f8cd980d8303ecc169e147109cf7f Mon Sep 17 00:00:00 2001
From: Yongjia Zhang <zhang_yong_jia@126.com>
Date: Fri, 18 Jul 2014 02:14:37 +0800
Subject: [PATCH] Add Gen IR IF, ELSE and ENDIF

Add Gen IR IF, ELSE and ENDIF to mark the strucutred region.

Signed-off-by: Yongjia Zhang <yongjia.zhang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
---
 backend/src/ir/instruction.cpp | 22 ++++++++++++++++++----
 backend/src/ir/instruction.hpp |  6 ++++++
 backend/src/ir/instruction.hxx |  3 +++
 3 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 435869e..f714ecf 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -345,7 +345,7 @@ namespace ir {
     {
     public:
       INLINE BranchInstruction(Opcode op, LabelIndex labelIndex, Register predicate) {
-        GBE_ASSERT(op == OP_BRA);
+        GBE_ASSERT(op == OP_BRA || op == OP_IF);
         this->opcode = op;
         this->predicate = predicate;
         this->labelIndex = labelIndex;
@@ -353,15 +353,15 @@ namespace ir {
         this->hasLabel = true;
       }
       INLINE BranchInstruction(Opcode op, LabelIndex labelIndex) {
-        GBE_ASSERT(op == OP_BRA);
-        this->opcode = OP_BRA;
+        GBE_ASSERT(op == OP_BRA || op == OP_ELSE || op == OP_ENDIF);
+        this->opcode = op;
         this->labelIndex = labelIndex;
         this->hasPredicate = false;
         this->hasLabel = true;
       }
       INLINE BranchInstruction(Opcode op) {
         GBE_ASSERT(op == OP_RET);
-        this->opcode = OP_RET;
+        this->opcode = op;
         this->hasPredicate = false;
         this->hasLabel = false;
       }
@@ -1590,6 +1590,20 @@ DECL_MEM_FN(GetImageInfoInstruction, const uint8_t, getImageIndex(void), getImag
     return internal::BranchInstruction(OP_BRA, labelIndex, pred).convert();
   }
 
+  // IF
+  Instruction IF(LabelIndex labelIndex, Register pred) {
+    return internal::BranchInstruction(OP_IF, labelIndex, pred).convert();
+  }
+
+  // ELSE
+  Instruction ELSE(LabelIndex labelIndex) {
+    return internal::BranchInstruction(OP_ELSE, labelIndex).convert();
+  }
+  // ENDIF
+  Instruction ENDIF(LabelIndex labelIndex) {
+    return internal::BranchInstruction(OP_ENDIF, labelIndex).convert();
+  }
+
   // RET
   Instruction RET(void) {
     return internal::BranchInstruction(OP_RET).convert();
diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp
index a29a734..5f0cb05 100644
--- a/backend/src/ir/instruction.hpp
+++ b/backend/src/ir/instruction.hpp
@@ -649,6 +649,12 @@ namespace ir {
   Instruction BRA(LabelIndex labelIndex);
   /*! (pred) bra labelIndex */
   Instruction BRA(LabelIndex labelIndex, Register pred);
+  /*! (pred) if labelIndex */
+  Instruction IF(LabelIndex labelIndex, Register pred);
+  /*! else labelIndex */
+  Instruction ELSE(LabelIndex labelIndex);
+  /*! endif */
+  Instruction ENDIF(LabelIndex labelIndex);
   /*! ret */
   Instruction RET(void);
   /*! load.type.space {dst1,...,dst_valueNum} offset value */
diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx
index 587517b..abc984f 100644
--- a/backend/src/ir/instruction.hxx
+++ b/backend/src/ir/instruction.hxx
@@ -93,3 +93,6 @@ DECL_INSN(UPSAMPLE_INT, BinaryInstruction)
 DECL_INSN(UPSAMPLE_LONG, BinaryInstruction)
 DECL_INSN(I64MADSAT, TernaryInstruction)
 DECL_INSN(MAD, TernaryInstruction)
+DECL_INSN(IF, BranchInstruction)
+DECL_INSN(ENDIF, BranchInstruction)
+DECL_INSN(ELSE, BranchInstruction)
-- 
2.7.4