From 7636c9a9297d82559a342d2c18a1205d7d7715c6 Mon Sep 17 00:00:00 2001 From: alex-t Date: Tue, 22 Mar 2022 13:13:15 +0100 Subject: [PATCH] [AMDGPU] use scalar shift for SALU users in frame index elimination In the frame index lowering we have to insert shift and add instructions to adjust stack object access. We need to take care of the stack object user kind and use scalar shift/add for scalar users. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D121524 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index d6b9c9f..3d7d56e 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -2272,7 +2272,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } else { MachineInstrBuilder MIB; if (!IsSALU) { - if (MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) { + if ((MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) != + nullptr) { // Reuse ResultReg in intermediate step. Register ScaledReg = ResultReg; -- 2.7.4