From 7625b3d03136f85d49571d484afcb6ae0cdfcfa8 Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Mon, 25 Mar 2019 15:55:59 +0800 Subject: [PATCH] clk: meson-tm2: add new clocks [1/1] PD#SWPL-5636 Problem: pcie and several clk81 clocks are newly added in tm2 SoC Solution: add pcie and several clk81 clocks Verify: test passed on ptm Change-Id: I8456d7fa8ffb6438e99d3f1cddee4a3ba846b933 Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,meson-clkc.txt | 1 + MAINTAINERS | 4 + arch/arm/boot/dts/amlogic/mesontm2.dtsi | 5 + arch/arm64/boot/dts/amlogic/mesontm2.dtsi | 4 + drivers/amlogic/clk/Makefile | 1 + drivers/amlogic/clk/tl1/tl1.c | 2 +- drivers/amlogic/clk/tl1/tl1.h | 8 +- drivers/amlogic/clk/tl1/tl1_clk-pll.c | 42 ++++ drivers/amlogic/clk/tm2/Makefile | 5 + drivers/amlogic/clk/tm2/tm2.c | 271 +++++++++++++++++++++ drivers/amlogic/clk/tm2/tm2.h | 37 +++ include/dt-bindings/clock/amlogic,tl1-clkc.h | 35 ++- 12 files changed, 407 insertions(+), 8 deletions(-) create mode 100644 drivers/amlogic/clk/tm2/Makefile create mode 100644 drivers/amlogic/clk/tm2/tm2.c create mode 100644 drivers/amlogic/clk/tm2/tm2.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt index d9b8a3d..27e3359 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt @@ -25,6 +25,7 @@ Required Properties: "amlogic,sm1-clkc-1" - for sm1 ee part1 clock "amlogic,sm1-clkc-2" - for sm1 ee part2 clock "amlogic,sm1-aoclkc" - for sm1 ao clock + "amlogic,tm2-clkc" - for tm2 additional ee clock - reg: physical base address of the clock controller and length of memory mapped region. diff --git a/MAINTAINERS b/MAINTAINERS index 7d3c7fa..04238a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14849,3 +14849,7 @@ AMLOGIC TM2 PINCTRL DRIVER M: Qianggui Song F: drivers/amlogic/pinctrl/pinctrl-meson-tm2.c F: include/dt-bindings/gpio/meson-tm2-gpio.h + +AMLOGIC MESON TM2 CLOCK DRIVER +M: Jian Hu +F: driver/amlogic/clk/tm2/* diff --git a/arch/arm/boot/dts/amlogic/mesontm2.dtsi b/arch/arm/boot/dts/amlogic/mesontm2.dtsi index 36fcea2..d8e7df7 100644 --- a/arch/arm/boot/dts/amlogic/mesontm2.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontm2.dtsi @@ -634,6 +634,11 @@ #clock-cells = <1>; reg = <0x0 0x3fc>; }; + + clkc1: clock-controller@1 { + compatible = "amlogic,tm2-clkc"; + #clock-cells = <1>; + }; };/* end of hiubus*/ audiobus: audiobus@0xff600000 { diff --git a/arch/arm64/boot/dts/amlogic/mesontm2.dtsi b/arch/arm64/boot/dts/amlogic/mesontm2.dtsi index 1c9da7a..be84c14 100644 --- a/arch/arm64/boot/dts/amlogic/mesontm2.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesontm2.dtsi @@ -615,6 +615,10 @@ #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3fc>; }; + clkc1: clock-controller@1 { + compatible = "amlogic,tm2-clkc"; + #clock-cells = <1>; + }; };/* end of hiubus*/ audiobus: audiobus@0xff600000 { diff --git a/drivers/amlogic/clk/Makefile b/drivers/amlogic/clk/Makefile index 95486a7..b848f0c 100644 --- a/drivers/amlogic/clk/Makefile +++ b/drivers/amlogic/clk/Makefile @@ -19,5 +19,6 @@ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a/ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12b/ obj-$(CONFIG_AMLOGIC_GX_CLK) += tl1/ obj-$(CONFIG_AMLOGIC_GX_CLK) += sm1/ +obj-$(CONFIG_AMLOGIC_GX_CLK) += tm2/ obj-$(CONFIG_AMLOGIC_M8B_CLK) += m8b/ diff --git a/drivers/amlogic/clk/tl1/tl1.c b/drivers/amlogic/clk/tl1/tl1.c index 472d945..c9d660c 100644 --- a/drivers/amlogic/clk/tl1/tl1.c +++ b/drivers/amlogic/clk/tl1/tl1.c @@ -687,7 +687,7 @@ static struct clk_hw *tl1_clk_hws[] = { [CLKID_BT656] = &tl1_bt656.hw, /*MPEG2 6*/ [CLKID_USB1_TO_DDR] = &tl1_usb1_to_ddr.hw, /*MPEG2 8*/ [CLKID_MMC_PCLK] = &tl1_mmc_pclk.hw, /*MPEG2 11*/ - [CLKID_HDCP22_PCLK] = &tl1_hdcp22_pclk.hw, /*MPEG2 13*/ + [CLKID_HDMIRX_TOP] = &tl1_hdcp22_pclk.hw, /*MPEG2 13*/ [CLKID_UART2] = &tl1_uart2.hw, /*MPEG2 15*/ [CLKID_TS] = &tl1_ts.hw, /*MPEG2 22*/ [CLKID_VPU_INTR] = &tl1_vpu_intr.hw, /*MPEG2 25*/ diff --git a/drivers/amlogic/clk/tl1/tl1.h b/drivers/amlogic/clk/tl1/tl1.h index 1241f87..94e9608 100644 --- a/drivers/amlogic/clk/tl1/tl1.h +++ b/drivers/amlogic/clk/tl1/tl1.h @@ -50,10 +50,10 @@ #define HHI_HIFI_PLL_CNTL6 0xec /* 0x3b offset in datasheet */ #define HHI_HIFI_PLL_STS 0xf0 /* 0x3c offset in datasheet very*/ -#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in datasheet */ -#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in datasheet */ -#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in datasheet */ -#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in datasheet */ +#define HHI_GCLK_MPEG0 0xc0 /* 0x30 offset in datasheet */ +#define HHI_GCLK_MPEG1 0xc4 /* 0x31 offset in datasheet */ +#define HHI_GCLK_MPEG2 0xc8 /* 0x32 offset in datasheet */ +#define HHI_GCLK_OTHER 0xd0 /* 0x34 offset in datasheet */ #define HHI_GCLK_AO 0x154 /* 0x55 offset in datasheet */ diff --git a/drivers/amlogic/clk/tl1/tl1_clk-pll.c b/drivers/amlogic/clk/tl1/tl1_clk-pll.c index b74f272..d724809 100644 --- a/drivers/amlogic/clk/tl1/tl1_clk-pll.c +++ b/drivers/amlogic/clk/tl1/tl1_clk-pll.c @@ -70,6 +70,19 @@ #define TL1_PLL_CNTL6 0x56540000 +#define TM2_PCIE_PLL_CNTL0_0 0x28060464 +#define TM2_PCIE_PLL_CNTL0_1 0x38060464 +#define TM2_PCIE_PLL_CNTL0_2 0x3c060464 +#define TM2_PCIE_PLL_CNTL0_3 0x1c060464 +#define TM2_PCIE_PLL_CNTL1 0x00000000 +#define TM2_PCIE_PLL_CNTL2 0x00001100 +#define TM2_PCIE_PLL_CNTL2_ 0x00001000 +#define TM2_PCIE_PLL_CNTL3 0x10058e00 +#define TM2_PCIE_PLL_CNTL4 0x000100c0 +#define TM2_PCIE_PLL_CNTL4_ 0x008100c0 +#define TM2_PCIE_PLL_CNTL5 0x68000048 +#define TM2_PCIE_PLL_CNTL5_ 0x68000068 + #define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) static unsigned long meson_tl1_pll_recalc_rate(struct clk_hw *hw, @@ -285,6 +298,35 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(TL1_PLL_CNTL6, cntlbase + (unsigned long)(6*4)); udelay(10); + } else if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) { + writel(TM2_PCIE_PLL_CNTL0_0, + cntlbase + (unsigned long)(0*4)); + writel(TM2_PCIE_PLL_CNTL0_1, + cntlbase + (unsigned long)(0*4)); + writel(TM2_PCIE_PLL_CNTL1, + cntlbase + (unsigned long)(1*4)); + writel(TM2_PCIE_PLL_CNTL2, + cntlbase + (unsigned long)(7*4)); + writel(TM2_PCIE_PLL_CNTL3, + cntlbase + (unsigned long)(8*4)); + writel(TM2_PCIE_PLL_CNTL4, + cntlbase + (unsigned long)(53*4)); + writel(TM2_PCIE_PLL_CNTL5, + cntlbase + (unsigned long)(54*4)); + writel(TM2_PCIE_PLL_CNTL5_, + cntlbase + (unsigned long)(54*4)); + udelay(20); + writel(TM2_PCIE_PLL_CNTL4_, + cntlbase + (unsigned long)(53*4)); + udelay(10); + /*set pcie_apll_afc_start bit*/ + writel(TM2_PCIE_PLL_CNTL0_2, + cntlbase + (unsigned long)(0*4)); + writel(TM2_PCIE_PLL_CNTL0_3, + cntlbase + (unsigned long)(0*4)); + udelay(10); + writel(TM2_PCIE_PLL_CNTL2_, + cntlbase + (unsigned long)(7*4)); } else { pr_err("%s: %s pll not found!!!\n", __func__, clk_hw_get_name(hw)); diff --git a/drivers/amlogic/clk/tm2/Makefile b/drivers/amlogic/clk/tm2/Makefile new file mode 100644 index 0000000..092e633 --- /dev/null +++ b/drivers/amlogic/clk/tm2/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for Meson TL1 clk +# + +obj-$(CONFIG_AMLOGIC_GX_CLK) += tm2.o diff --git a/drivers/amlogic/clk/tm2/tm2.c b/drivers/amlogic/clk/tm2/tm2.c new file mode 100644 index 0000000..5621ff5 --- /dev/null +++ b/drivers/amlogic/clk/tm2/tm2.c @@ -0,0 +1,271 @@ +/* + * drivers/amlogic/clk/tm2/tm2.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "../tl1/tl1.h" +#include "tm2.h" + +static const struct pll_rate_table tm2_pcie_pll_rate_table[] = { + PLL_RATE(100000000, 100, 1, 6), + { /* sentinel */ }, +}; + +static struct meson_clk_pll tm2_pcie_pll = { + .m = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 10, + .width = 5, + }, + .od = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 16, + .width = 5, + }, + .frac = { + .reg_off = HHI_PCIE_PLL_CNTL1, + .shift = 0, + .width = 12, + }, + .rate_table = tm2_pcie_pll_rate_table, + .rate_count = ARRAY_SIZE(tm2_pcie_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll", + .ops = &meson_tl1_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate tm2_pcie01_enable = { + .reg = (void *)HHI_PCIE_PLL_CNTL1, + .bit_idx = 29, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "tm2_pcie01", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "pcie_pll" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_gate tm2_pcie0_gate = { + .reg = (void *)HHI_PCIE_PLL_CNTL1, + .bit_idx = 28, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "tm2_pcie0_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "tm2_pcie01" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_gate tm2_pcie1_gate = { + .reg = (void *)HHI_PCIE_PLL_CNTL5, + .bit_idx = 3, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "tm2_pcie1_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "tm2_pcie01" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* clk81 gate for tm2 */ +static MESON_GATE(tm2_vipnanoq, HHI_GCLK_MPEG1, 19); +static MESON_GATE(tm2_pcie1, HHI_GCLK_MPEG1, 24); +static MESON_GATE(tm2_pcie1phy, HHI_GCLK_MPEG1, 27); +static MESON_GATE(tm2_parserl, HHI_GCLK_MPEG1, 28); +static MESON_GATE(tm2_hdcp22_pclk, HHI_GCLK_MPEG2, 3); +static MESON_GATE(tm2_hdmitx_pclk, HHI_GCLK_MPEG2, 4); +static MESON_GATE(tm2_pcie0, HHI_GCLK_MPEG2, 6); +static MESON_GATE(tm2_pcie0phy, HHI_GCLK_MPEG2, 7); +static MESON_GATE(tm2_hdmirx_axi_pclk, HHI_GCLK_MPEG2, 12); +static MESON_GATE(tm2_dspb, HHI_GCLK_MPEG2, 26); +static MESON_GATE(tm2_dspa, HHI_GCLK_MPEG2, 27); + +PNAME(dsp_parent_names) = { "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", "xtal", "gp0_pll", "gp1_pll", "hifi_pll" }; + +static MUX(dspa_clk_a_mux, HHI_DSP_CLK_CNTL, 0x7, 4, + dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(dspa_clk_a_div, HHI_DSP_CLK_CNTL, 0, 4, "dspa_clk_a_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); +static GATE(dspa_clk_a_gate, HHI_DSP_CLK_CNTL, 7, "dspa_clk_a_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); + +static MUX(dspa_clk_b_mux, HHI_DSP_CLK_CNTL, 0x7, 12, + dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(dspa_clk_b_div, HHI_DSP_CLK_CNTL, 8, 4, "dspa_clk_b_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); +static GATE(dspa_clk_b_gate, HHI_DSP_CLK_CNTL, 7, "dspa_clk_b_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); + +PNAME(dspa_parent_names) = { "dspa_clk_a_gate", + "dspa_clk_b_gate" }; + +static MESON_MUX(dspa_clk_mux, HHI_DSP_CLK_CNTL, 0x1, 15, + dspa_parent_names, CLK_GET_RATE_NOCACHE); + + +static MUX(dspb_clk_a_mux, HHI_DSP_CLK_CNTL, 0x7, 20, + dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(dspb_clk_a_div, HHI_DSP_CLK_CNTL, 16, 4, "dspb_clk_a_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); +static GATE(dspb_clk_a_gate, HHI_SD_EMMC_CLK_CNTL, 23, "dspb_clk_a_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); + +static MUX(dspb_clk_b_mux, HHI_DSP_CLK_CNTL, 0x7, 28, + dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(dspb_clk_b_div, HHI_DSP_CLK_CNTL, 24, 4, "dspb_clk_b_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); +static GATE(dspb_clk_b_gate, HHI_DSP_CLK_CNTL, 23, "dspb_clk_b_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); + +PNAME(dspb_parent_names) = { "dspb_clk_a_gate", + "dspb_clk_b_gate" }; + +static MESON_MUX(dspb_clk_mux, HHI_VPU_CLKC_CNTL, 0x1, 31, + dspb_parent_names, CLK_GET_RATE_NOCACHE); + +static struct clk_gate *tm2_clk_gates[] = { + &tm2_vipnanoq, + &tm2_pcie1, + &tm2_pcie1phy, + &tm2_parserl, + &tm2_hdcp22_pclk, + &tm2_hdmitx_pclk, + &tm2_pcie0phy, + &tm2_hdmirx_axi_pclk, + &tm2_dspb, + &tm2_dspa, + &dspa_clk_a_gate, + &dspa_clk_b_gate, + &dspb_clk_a_gate, + &dspb_clk_b_gate, + &tm2_pcie0_gate, + &tm2_pcie1_gate, + &tm2_pcie0, + &tm2_pcie01_enable, +}; + +static struct clk_mux *tm2_clk_mux[] = { + &dspa_clk_a_mux, + &dspa_clk_b_mux, + &dspb_clk_a_mux, + &dspb_clk_b_mux, + &dspa_clk_mux, + &dspb_clk_mux, +}; + +static struct clk_divider *tm2_clk_divs[] = { + &dspa_clk_a_div, + &dspa_clk_b_div, + &dspb_clk_a_div, + &dspb_clk_b_div, +}; + +/* Array of all clocks provided by this provider */ +static struct clk_hw *tm2_clk_hws[] = { + [CLKID_PCIE_PLL] = &tm2_pcie_pll.hw, + [CLKID_VIPNANOQ] = &tm2_vipnanoq.hw, + [CLKID_PCIE0] = &tm2_pcie0.hw, + [CLKID_PCIE1] = &tm2_pcie1.hw, + [CLKID_PCIE1PHY] = &tm2_pcie1phy.hw, + [CLKID_PARSER1] = &tm2_parserl.hw, + [CLKID_HDCP22_PCLK] = &tm2_hdcp22_pclk.hw, + [CLKID_HDMITX_PCLK] = &tm2_hdmitx_pclk.hw, + [CLKID_PCIE0PHY] = &tm2_pcie0phy.hw, + [CLKID_HDMITX_AXI_PCLK] = &tm2_hdmirx_axi_pclk.hw, + [CLKID_DSPB] = &tm2_dspb.hw, + [CLKID_DSPA] = &tm2_dspa.hw, + [CLKID_DSPA_MUX_A] = &dspa_clk_a_mux.hw, + [CLKID_DSPA_DIV_A] = &dspa_clk_a_div.hw, + [CLKID_DSPA_GATE_A] = &dspa_clk_a_gate.hw, + [CLKID_DSPA_MUX_B] = &dspa_clk_b_mux.hw, + [CLKID_DSPA_DIV_B] = &dspa_clk_b_div.hw, + [CLKID_DSPA_GATE_B] = &dspa_clk_b_gate.hw, + [CLKID_DSPA_MUX] = &dspa_clk_mux.hw, + [CLKID_DSPB_MUX_A] = &dspb_clk_a_mux.hw, + [CLKID_DSPB_DIV_A] = &dspb_clk_a_div.hw, + [CLKID_DSPB_GATE_A] = &dspb_clk_a_gate.hw, + [CLKID_DSPB_MUX_B] = &dspb_clk_b_mux.hw, + [CLKID_DSPB_DIV_B] = &dspb_clk_b_div.hw, + [CLKID_DSPB_GATE_B] = &dspb_clk_b_gate.hw, + [CLKID_DSPB_MUX] = &dspb_clk_mux.hw, + [CLKID_PCIE01_ENABLE] = &tm2_pcie01_enable.hw, + [CLKID_PCIE0_GATE] = &tm2_pcie0_gate.hw, + [CLKID_PCIE1_GATE] = &tm2_pcie1_gate.hw, +}; + +static void __init tm2_clkc_init(struct device_node *np) +{ + int clkid, i; + + if (!clk_base) { + pr_err("tm2 clock basic clock driver not prepare\n"); + WARN_ON(IS_ERR(clk_base)); + return; + } + + /* Populate base address for pcie pll */ + tm2_pcie_pll.base = clk_base; + + /* Populate base address for media muxes */ + for (i = 0; i < ARRAY_SIZE(tm2_clk_mux); i++) + tm2_clk_mux[i]->reg = clk_base + + (unsigned long)tm2_clk_mux[i]->reg; + + /* Populate base address for media divs */ + for (i = 0; i < ARRAY_SIZE(tm2_clk_divs); i++) + tm2_clk_divs[i]->reg = clk_base + + (unsigned long)tm2_clk_divs[i]->reg; + + /* Populate base address for gates */ + for (i = 0; i < ARRAY_SIZE(tm2_clk_gates); i++) + tm2_clk_gates[i]->reg = clk_base + + (unsigned long)tm2_clk_gates[i]->reg; + + /* register tm2 clks, pcie pll is the first clock index */ + for (clkid = CLKID_PCIE_PLL; clkid < GATE_BASE0; clkid++) { + if (tm2_clk_hws[clkid]) { + clks[clkid] = clk_register(NULL, tm2_clk_hws[clkid]); + WARN_ON(IS_ERR(clks[clkid])); + } + } +} + +CLK_OF_DECLARE(tm2, "amlogic,tm2-clkc", tm2_clkc_init); diff --git a/drivers/amlogic/clk/tm2/tm2.h b/drivers/amlogic/clk/tm2/tm2.h new file mode 100644 index 0000000..128fcf7 --- /dev/null +++ b/drivers/amlogic/clk/tm2/tm2.h @@ -0,0 +1,37 @@ +/* + * drivers/amlogic/clk/tm2/tm2.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __TM2_H +#define __TM2_H + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define HHI_PCIE_PLL_CNTL0 0x94 /* 0x25 offset in data sheet */ +#define HHI_PCIE_PLL_CNTL1 0x98 /* 0x26 offset in data sheet */ +#define HHI_PCIE_PLL_CNTL2 0xb0 /* 0x2c offset in data sheet */ +#define HHI_PCIE_PLL_CNTL3 0xb4 /* 0x2d offset in data sheet */ +#define HHI_PCIE_PLL_CNTL4 0x168 /* 0x5a offset in data sheet */ +#define HHI_PCIE_PLL_CNTL5 0x16c /* 0x5b offset in data sheet */ +#define HHI_PCIE_PLL_STS 0x170 /* 0x5c offset in data sheet */ +#define HHI_DSP_CLK_CNTL 0x3f0 /* 0xfc offset in data sheet */ + +#endif /* __TL1_H */ diff --git a/include/dt-bindings/clock/amlogic,tl1-clkc.h b/include/dt-bindings/clock/amlogic,tl1-clkc.h index cf0bbb0..7e4f174 100644 --- a/include/dt-bindings/clock/amlogic,tl1-clkc.h +++ b/include/dt-bindings/clock/amlogic,tl1-clkc.h @@ -48,9 +48,38 @@ #define CLKID_CPU_FCLK_P 24 #define CLKID_CPU_CLK 25 /*#define CLKID_ADC_PLL 24*/ - +#define CLKID_PCIE_PLL 26 +#define CLKID_VIPNANOQ 27 +#define CLKID_PCIE1 28 +#define CLKID_PCIE0PHY 29 +#define CLKID_PCIE1PHY 30 +#define CLKID_PARSER1 31 +#define CLKID_HDCP22_PCLK 32 +#define CLKID_HDMITX_PCLK 33 +#define CLKID_HDMITX_AXI_PCLK 34 +#define CLKID_DSPB 35 +#define CLKID_DSPA 36 +/* dsp clocks */ +#define CLKID_DSPA_MUX_A 37 +#define CLKID_DSPA_DIV_A 38 +#define CLKID_DSPA_GATE_A 39 +#define CLKID_DSPA_MUX_B 40 +#define CLKID_DSPA_DIV_B 41 +#define CLKID_DSPA_GATE_B 42 +#define CLKID_DSPA_MUX 43 +#define CLKID_DSPB_MUX_A 44 +#define CLKID_DSPB_DIV_A 45 +#define CLKID_DSPB_GATE_A 46 +#define CLKID_DSPB_MUX_B 47 +#define CLKID_DSPB_DIV_B 48 +#define CLKID_DSPB_GATE_B 49 +#define CLKID_DSPB_MUX 50 +#define CLKID_PCIE0_GATE 51 +#define CLKID_PCIE1_GATE 52 +#define CLKID_PCIE0 53 +#define CLKID_PCIE01_ENABLE 54 /*HHI_GCLK_MPEG0: 0x50*/ -#define GATE_BASE0 (26) +#define GATE_BASE0 55 #define CLKID_DDR (GATE_BASE0 + 0) #define CLKID_DOS (GATE_BASE0 + 1) @@ -102,7 +131,7 @@ #define CLKID_BT656 (GATE_BASE2 + 2) #define CLKID_USB1_TO_DDR (GATE_BASE2 + 3) #define CLKID_MMC_PCLK (GATE_BASE2 + 4) -#define CLKID_HDCP22_PCLK (GATE_BASE0 + 5) +#define CLKID_HDMIRX_TOP (GATE_BASE0 + 5) #define CLKID_UART2 (GATE_BASE2 + 6) #define CLKID_TS (GATE_BASE2 + 7) #define CLKID_VPU_INTR (GATE_BASE2 + 8) -- 2.7.4