From 75a4e52580c047b8f5527f79a93cb3daea772968 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@lowrisc.org>
Date: Wed, 18 Apr 2018 16:43:03 +0000
Subject: [PATCH] [RISCV] Add specific tests for materialising imm32hi20
 constants

i.e. constants that can be materialised with a single lui, as the lower 12
bits are zero.

llvm-svn: 330274
---
 llvm/test/CodeGen/RISCV/imm.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index dca1c5e..b9e2f8a 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -45,3 +45,19 @@ define i32 @neg_i32() nounwind {
 ; RV32I-NEXT:    ret
   ret i32 -559038737
 }
+
+define i32 @pos_i32_hi20_only() nounwind {
+; RV32I-LABEL: pos_i32_hi20_only:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 16
+; RV32I-NEXT:    ret
+  ret i32 65536
+}
+
+define i32 @neg_i32_hi20_only() nounwind {
+; RV32I-LABEL: neg_i32_hi20_only:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 1048560
+; RV32I-NEXT:    ret
+  ret i32 -65536
+}
-- 
2.7.4