From 7568b106718165feacdf411f1b8f95ae4263456a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 8 Nov 2015 10:44:19 +1000 Subject: [PATCH] drm/nouveau/nvif: split out display interface definitions Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/cl0046.h | 28 +++ drivers/gpu/drm/nouveau/include/nvif/cl5070.h | 99 ++++++++ drivers/gpu/drm/nouveau/include/nvif/cl507a.h | 11 + drivers/gpu/drm/nouveau/include/nvif/cl507b.h | 11 + drivers/gpu/drm/nouveau/include/nvif/cl507c.h | 12 + drivers/gpu/drm/nouveau/include/nvif/cl507d.h | 11 + drivers/gpu/drm/nouveau/include/nvif/cl507e.h | 12 + drivers/gpu/drm/nouveau/include/nvif/class.h | 258 ++++----------------- drivers/gpu/drm/nouveau/nouveau_connector.c | 1 + drivers/gpu/drm/nouveau/nouveau_display.c | 1 + drivers/gpu/drm/nouveau/nv50_display.c | 6 + drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/basenv50.c | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/channv50.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/corenv50.c | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/piornv50.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c | 3 +- .../gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c | 2 +- 30 files changed, 261 insertions(+), 222 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl0046.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl5070.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl507a.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl507b.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl507c.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl507d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/cl507e.h diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0046.h b/drivers/gpu/drm/nouveau/include/nvif/cl0046.h new file mode 100644 index 0000000..a6a71f4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0046.h @@ -0,0 +1,28 @@ +#ifndef __NVIF_CL0046_H__ +#define __NVIF_CL0046_H__ + +#define NV04_DISP_NTFY_VBLANK 0x00 +#define NV04_DISP_NTFY_CONN 0x01 + +struct nv04_disp_mthd_v0 { + __u8 version; +#define NV04_DISP_SCANOUTPOS 0x00 + __u8 method; + __u8 head; + __u8 pad03[5]; +}; + +struct nv04_disp_scanoutpos_v0 { + __u8 version; + __u8 pad01[7]; + __s64 time[2]; + __u16 vblanks; + __u16 vblanke; + __u16 vtotal; + __u16 vline; + __u16 hblanks; + __u16 hblanke; + __u16 htotal; + __u16 hline; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h new file mode 100644 index 0000000..d15c296 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h @@ -0,0 +1,99 @@ +#ifndef __NVIF_CL5070_H__ +#define __NVIF_CL5070_H__ + +#define NV50_DISP_MTHD 0x00 + +struct nv50_disp_mthd_v0 { + __u8 version; +#define NV50_DISP_SCANOUTPOS 0x00 + __u8 method; + __u8 head; + __u8 pad03[5]; +}; + +struct nv50_disp_scanoutpos_v0 { + __u8 version; + __u8 pad01[7]; + __s64 time[2]; + __u16 vblanks; + __u16 vblanke; + __u16 vtotal; + __u16 vline; + __u16 hblanks; + __u16 hblanke; + __u16 htotal; + __u16 hline; +}; + +struct nv50_disp_mthd_v1 { + __u8 version; +#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 +#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 +#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 +#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 +#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 +#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 +#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 +#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 + __u8 method; + __u16 hasht; + __u16 hashm; + __u8 pad06[2]; +}; + +struct nv50_disp_dac_pwr_v0 { + __u8 version; + __u8 state; + __u8 data; + __u8 vsync; + __u8 hsync; + __u8 pad05[3]; +}; + +struct nv50_disp_dac_load_v0 { + __u8 version; + __u8 load; + __u8 pad02[2]; + __u32 data; +}; + +struct nv50_disp_sor_pwr_v0 { + __u8 version; + __u8 state; + __u8 pad02[6]; +}; + +struct nv50_disp_sor_hda_eld_v0 { + __u8 version; + __u8 pad01[7]; + __u8 data[]; +}; + +struct nv50_disp_sor_hdmi_pwr_v0 { + __u8 version; + __u8 state; + __u8 max_ac_packet; + __u8 rekey; + __u8 pad04[4]; +}; + +struct nv50_disp_sor_lvds_script_v0 { + __u8 version; + __u8 pad01[1]; + __u16 script; + __u8 pad04[4]; +}; + +struct nv50_disp_sor_dp_pwr_v0 { + __u8 version; + __u8 state; + __u8 pad02[6]; +}; + +struct nv50_disp_pior_pwr_v0 { + __u8 version; + __u8 state; + __u8 type; + __u8 pad03[5]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507a.h b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h new file mode 100644 index 0000000..12e0643 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL507A_H__ +#define __NVIF_CL507A_H__ + +struct nv50_disp_cursor_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; +}; + +#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507b.h b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h new file mode 100644 index 0000000..99e9d8c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL507B_H__ +#define __NVIF_CL507B_H__ + +struct nv50_disp_overlay_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; +}; + +#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507c.h b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h new file mode 100644 index 0000000..6af70db --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h @@ -0,0 +1,12 @@ +#ifndef __NVIF_CL507C_H__ +#define __NVIF_CL507C_H__ + +struct nv50_disp_base_channel_dma_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; + __u64 pushbuf; +}; + +#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507d.h b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h new file mode 100644 index 0000000..5ab0c9e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL507D_H__ +#define __NVIF_CL507D_H__ + +struct nv50_disp_core_channel_dma_v0 { + __u8 version; + __u8 pad01[7]; + __u64 pushbuf; +}; + +#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507e.h b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h new file mode 100644 index 0000000..c06209f --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h @@ -0,0 +1,12 @@ +#ifndef __NVIF_CL507E_H__ +#define __NVIF_CL507E_H__ + +struct nv50_disp_overlay_channel_dma_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; + __u64 pushbuf; +}; + +#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 65b7e45..aa1e063 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -24,7 +24,7 @@ #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 -#define NV04_DISP 0x00000046 +#define NV04_DISP /* cl0046.h */ 0x00000046 #define NV03_CHANNEL_DMA 0x0000006b #define NV10_CHANNEL_DMA 0x0000006e @@ -39,59 +39,59 @@ #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f #define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f -#define NV50_DISP 0x00005070 -#define G82_DISP 0x00008270 -#define GT200_DISP 0x00008370 -#define GT214_DISP 0x00008570 -#define GT206_DISP 0x00008870 -#define GF110_DISP 0x00009070 -#define GK104_DISP 0x00009170 -#define GK110_DISP 0x00009270 -#define GM107_DISP 0x00009470 -#define GM204_DISP 0x00009570 +#define NV50_DISP /* cl5070.h */ 0x00005070 +#define G82_DISP /* cl5070.h */ 0x00008270 +#define GT200_DISP /* cl5070.h */ 0x00008370 +#define GT214_DISP /* cl5070.h */ 0x00008570 +#define GT206_DISP /* cl5070.h */ 0x00008870 +#define GF110_DISP /* cl5070.h */ 0x00009070 +#define GK104_DISP /* cl5070.h */ 0x00009170 +#define GK110_DISP /* cl5070.h */ 0x00009270 +#define GM107_DISP /* cl5070.h */ 0x00009470 +#define GM204_DISP /* cl5070.h */ 0x00009570 #define NV31_MPEG 0x00003174 #define G82_MPEG 0x00008274 #define NV74_VP2 0x00007476 -#define NV50_DISP_CURSOR 0x0000507a -#define G82_DISP_CURSOR 0x0000827a -#define GT214_DISP_CURSOR 0x0000857a -#define GF110_DISP_CURSOR 0x0000907a -#define GK104_DISP_CURSOR 0x0000917a - -#define NV50_DISP_OVERLAY 0x0000507b -#define G82_DISP_OVERLAY 0x0000827b -#define GT214_DISP_OVERLAY 0x0000857b -#define GF110_DISP_OVERLAY 0x0000907b -#define GK104_DISP_OVERLAY 0x0000917b - -#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c -#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c -#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c -#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c -#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c -#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c -#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c - -#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d -#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d -#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d -#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d -#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d -#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d -#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d -#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d -#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d -#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d - -#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e -#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e -#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e -#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e -#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e -#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e +#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a +#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a +#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a +#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a +#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a + +#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b +#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b +#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b +#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b +#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b + +#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c +#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c +#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c +#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c +#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c +#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c +#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c + +#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d +#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d +#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d +#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d +#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d +#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d +#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d +#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d +#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d +#define GM204_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d + +#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e +#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e +#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e +#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e +#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e +#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e #define FERMI_A /* cl9097.h */ 0x00009097 #define FERMI_B /* cl9097.h */ 0x00009197 @@ -452,166 +452,4 @@ struct kepler_channel_gpfifo_a_v0 { __u64 ioffset; __u64 vm; }; - -/******************************************************************************* - * legacy display - ******************************************************************************/ - -#define NV04_DISP_NTFY_VBLANK 0x00 -#define NV04_DISP_NTFY_CONN 0x01 - -struct nv04_disp_mthd_v0 { - __u8 version; -#define NV04_DISP_SCANOUTPOS 0x00 - __u8 method; - __u8 head; - __u8 pad03[5]; -}; - -struct nv04_disp_scanoutpos_v0 { - __u8 version; - __u8 pad01[7]; - __s64 time[2]; - __u16 vblanks; - __u16 vblanke; - __u16 vtotal; - __u16 vline; - __u16 hblanks; - __u16 hblanke; - __u16 htotal; - __u16 hline; -}; - -/******************************************************************************* - * display - ******************************************************************************/ - -#define NV50_DISP_MTHD 0x00 - -struct nv50_disp_mthd_v0 { - __u8 version; -#define NV50_DISP_SCANOUTPOS 0x00 - __u8 method; - __u8 head; - __u8 pad03[5]; -}; - -struct nv50_disp_mthd_v1 { - __u8 version; -#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 -#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 -#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 -#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 -#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 -#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 -#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 -#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 - __u8 method; - __u16 hasht; - __u16 hashm; - __u8 pad06[2]; -}; - -struct nv50_disp_dac_pwr_v0 { - __u8 version; - __u8 state; - __u8 data; - __u8 vsync; - __u8 hsync; - __u8 pad05[3]; -}; - -struct nv50_disp_dac_load_v0 { - __u8 version; - __u8 load; - __u8 pad02[2]; - __u32 data; -}; - -struct nv50_disp_sor_pwr_v0 { - __u8 version; - __u8 state; - __u8 pad02[6]; -}; - -struct nv50_disp_sor_hda_eld_v0 { - __u8 version; - __u8 pad01[7]; - __u8 data[]; -}; - -struct nv50_disp_sor_hdmi_pwr_v0 { - __u8 version; - __u8 state; - __u8 max_ac_packet; - __u8 rekey; - __u8 pad04[4]; -}; - -struct nv50_disp_sor_lvds_script_v0 { - __u8 version; - __u8 pad01[1]; - __u16 script; - __u8 pad04[4]; -}; - -struct nv50_disp_sor_dp_pwr_v0 { - __u8 version; - __u8 state; - __u8 pad02[6]; -}; - -struct nv50_disp_pior_pwr_v0 { - __u8 version; - __u8 state; - __u8 type; - __u8 pad03[5]; -}; - -/* core */ -struct nv50_disp_core_channel_dma_v0 { - __u8 version; - __u8 pad01[7]; - __u64 pushbuf; -}; - -#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/* cursor immediate */ -struct nv50_disp_cursor_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; -}; - -#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 - -/* base */ -struct nv50_disp_base_channel_dma_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/* overlay */ -struct nv50_disp_overlay_channel_dma_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/* overlay immediate */ -struct nv50_disp_overlay_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; -}; - -#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 8d00d00..40612e7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -42,6 +42,7 @@ #include "nouveau_encoder.h" #include "nouveau_crtc.h" +#include #include MODULE_PARM_DESC(tv_disable, "Disable TV-out detection"); diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 18676b8..24be27d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -39,6 +39,7 @@ #include "nouveau_fence.h" +#include #include static int diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 74247e1..a934a7e 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -31,6 +31,12 @@ #include #include +#include +#include +#include +#include +#include +#include #include "nouveau_drm.h" #include "nouveau_dma.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 44b6771..9ac1638 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -32,6 +32,7 @@ #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c index 1fd89ed..23e3d43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c @@ -27,6 +27,7 @@ #include #include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index 01803c0..41d0ad2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c index db4a9b3..6901b71 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c @@ -28,6 +28,7 @@ #include #include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c index 225858e..3e9d27e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c @@ -27,6 +27,7 @@ #include #include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c index 9bfa9e7..4a3e0f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c index af99efb..ae7343d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c @@ -29,7 +29,7 @@ #include #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c index c1590b7..e6390e9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c index ee9e800..3eca62a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c @@ -25,7 +25,7 @@ #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c index b5af025..62ca1fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c @@ -25,7 +25,7 @@ #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c index 110dc19..efba0e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c @@ -25,7 +25,7 @@ #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c index 61237db..472444c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c @@ -26,7 +26,7 @@ #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c index cd888a1e..8e9a064 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c @@ -27,6 +27,7 @@ #include #include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c index 6fa296c..503e9b5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c @@ -27,6 +27,7 @@ #include #include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c index ab524bd..dcd1836 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c index 8591726..09d1206 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c @@ -29,6 +29,7 @@ #include #include +#include #include int @@ -39,7 +40,7 @@ gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0) const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300)); const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300)); union { - struct nv04_disp_scanoutpos_v0 v0; + struct nv50_disp_scanoutpos_v0 v0; } *args = data; int ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c index 2be8463..d73f1c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c @@ -27,6 +27,7 @@ #include #include +#include #include struct nv04_disp_root { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c index 06fb24d..2aba84d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c @@ -29,6 +29,7 @@ #include #include +#include #include int @@ -39,7 +40,7 @@ nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0) const u32 blanks = nvkm_rd32(device, 0x610af4 + (head * 0x540)); const u32 total = nvkm_rd32(device, 0x610afc + (head * 0x540)); union { - struct nv04_disp_scanoutpos_v0 v0; + struct nv50_disp_scanoutpos_v0 v0; } *args = data; int ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c index 29e0d2a..6e8c954 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include int -- 2.7.4