From 74b078294ff974599416f4e961861dd0e8396748 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 29 Oct 2020 14:16:12 -0700 Subject: [PATCH] [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW This combine makes two calls to SimplifyDemandedBits, one for the LHS and one for the RHS. If the LHS call returns true, we don't make the RHS call. When SimplifyDemandedBits makes a change, it will add the nodes around the change to the DAG combiner worklist. If the simplification happens on the first recursion step, the N will get added to the worklist. But if the simplification happens deeper in the recursion, then N will not be revisited until the next time the DAG combiner runs. This patch explicitly addes N to the worklist anytime a Simplification is made. Without this we might miss additional simplifications on the LHS or never simplify the RHS. Special care also needs to be taken to not add N if it has been CSEd by the simplification. There are similar examples in DAGCombiner and the X86 target, but I don't have a test for it for RISC-V. I've also returned SDValue(N, 0) instead of SDValue() so DAGCombiner knows a change was made and will update its Statistic variable. The test here was constructed so that 2 simplifications happen to the LHS. Without this fix one happens in the post type legalization DAG combine and the other happens after LegalizeDAG. This prevents the RHS from ever being simplified causing the left and right shift to clear the upper 32 bits of the RHS to be left behind. Differential Revision: https://reviews.llvm.org/D90339 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++++++--- llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll | 2 -- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 773a098..5916bb3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1071,9 +1071,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, SDValue RHS = N->getOperand(1); APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32); APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5); - if ((SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI)) || - (SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI))) - return SDValue(); + if (SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI) || + SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) + DCI.AddToWorklist(N); + return SDValue(N, 0); + } break; } case RISCVISD::FMV_X_ANYEXTW_RV64: { diff --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll index 319270c..671f90b 100644 --- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll @@ -14,8 +14,6 @@ define i32 @foo(i32 %x, i32 %y, i32 %z) { ; CHECK-NEXT: mul a0, a0, a0 ; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: addi a0, a0, 1 -; CHECK-NEXT: slli a1, a1, 32 -; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: sllw a0, a0, a1 ; CHECK-NEXT: ret %b = mul i32 %x, %x -- 2.7.4