From 7459781bd9bd6c106dfa83dbf3179bff6aae2d54 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 12 Feb 2020 17:50:52 -0500 Subject: [PATCH] X86: Generate mir checks in sqrt test --- llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll | 78 ++++++++++++++++-------------- 1 file changed, 43 insertions(+), 35 deletions(-) diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll index 6abf34c..152833e 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll @@ -1,48 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s declare float @llvm.sqrt.f32(float) #0 define float @foo(float %f) #0 { -; CHECK: {{name: *foo}} -; CHECK: body: -; CHECK: %0:fr32 = COPY $xmm0 -; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0 -; CHECK: %3:fr32 = nofpexcept VMULSSrr %0, %1 -; CHECK: %4:fr32 = VMOVSSrm -; CHECK: %5:fr32 = nofpexcept VFMADD213SSr %1, killed %3, %4 -; CHECK: %6:fr32 = VMOVSSrm -; CHECK: %7:fr32 = nofpexcept VMULSSrr %1, %6 -; CHECK: %8:fr32 = nofpexcept VMULSSrr killed %7, killed %5 -; CHECK: %9:fr32 = nofpexcept VMULSSrr %0, %8 -; CHECK: %10:fr32 = nofpexcept VFMADD213SSr %8, %9, %4 -; CHECK: %11:fr32 = nofpexcept VMULSSrr %9, %6 -; CHECK: %12:fr32 = nofpexcept VMULSSrr killed %11, killed %10 -; CHECK: %14:fr32 = FsFLD0SS -; CHECK: %15:fr32 = nofpexcept VCMPSSrr %0, killed %14, 0 -; CHECK: %17:vr128 = VPANDNrr killed %16, killed %13 -; CHECK: $xmm0 = COPY %18 -; CHECK: RET 0, $xmm0 + ; CHECK-LABEL: name: foo + ; CHECK: bb.0 (%ir-block.0): + ; CHECK: liveins: $xmm0 + ; CHECK: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0 + ; CHECK: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF + ; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = VRSQRTSSr killed [[DEF]], [[COPY]] + ; CHECK: %3:fr32 = nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr + ; CHECK: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool) + ; CHECK: %5:fr32 = nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed %3, [[VMOVSSrm_alt]], implicit $mxcsr + ; CHECK: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load 4 from constant-pool) + ; CHECK: %7:fr32 = nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr + ; CHECK: %8:fr32 = nofpexcept VMULSSrr killed %7, killed %5, implicit $mxcsr + ; CHECK: %9:fr32 = nofpexcept VMULSSrr [[COPY]], %8, implicit $mxcsr + ; CHECK: %10:fr32 = nofpexcept VFMADD213SSr %8, %9, [[VMOVSSrm_alt]], implicit $mxcsr + ; CHECK: %11:fr32 = nofpexcept VMULSSrr %9, [[VMOVSSrm_alt1]], implicit $mxcsr + ; CHECK: %12:fr32 = nofpexcept VMULSSrr killed %11, killed %10, implicit $mxcsr + ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %12 + ; CHECK: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS + ; CHECK: %15:fr32 = nofpexcept VCMPSSrr [[COPY]], killed [[FsFLD0SS]], 0, implicit $mxcsr + ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY %15 + ; CHECK: [[VPANDNrr:%[0-9]+]]:vr128 = VPANDNrr killed [[COPY2]], killed [[COPY1]] + ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[VPANDNrr]] + ; CHECK: $xmm0 = COPY [[COPY3]] + ; CHECK: RET 0, $xmm0 %call = tail call float @llvm.sqrt.f32(float %f) #1 ret float %call } define float @rfoo(float %f) #0 { -; CHECK: {{name: *rfoo}} -; CHECK: body: | -; CHECK: %0:fr32 = COPY $xmm0 -; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0 -; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %1 -; CHECK: %4:fr32 = VMOVSSrm -; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %1, killed %3, %4 -; CHECK: %6:fr32 = VMOVSSrm -; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %1, %6 -; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed %5 -; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %8 -; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %9, %4 -; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, %6 -; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, killed %10 -; CHECK: $xmm0 = COPY %12 -; CHECK: RET 0, $xmm0 + ; CHECK-LABEL: name: rfoo + ; CHECK: bb.0 (%ir-block.0): + ; CHECK: liveins: $xmm0 + ; CHECK: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0 + ; CHECK: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF + ; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = VRSQRTSSr killed [[DEF]], [[COPY]] + ; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr + ; CHECK: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool) + ; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed %3, [[VMOVSSrm_alt]], implicit $mxcsr + ; CHECK: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load 4 from constant-pool) + ; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr + ; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed %5, implicit $mxcsr + ; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], %8, implicit $mxcsr + ; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %9, [[VMOVSSrm_alt]], implicit $mxcsr + ; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, [[VMOVSSrm_alt1]], implicit $mxcsr + ; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, killed %10, implicit $mxcsr + ; CHECK: $xmm0 = COPY %12 + ; CHECK: RET 0, $xmm0 %sqrt = tail call float @llvm.sqrt.f32(float %f) %div = fdiv fast float 1.0, %sqrt ret float %div -- 2.7.4