From 7432fb2c784691eb85b5996e0922b55389b43b6e Mon Sep 17 00:00:00 2001 From: Simon Wallis Date: Mon, 8 Jun 2020 08:10:42 +0100 Subject: [PATCH] [ARM][XO] Execute-only miscompiles double literals for big-endian Summary: With -mbig-endian -mexecute-only and targeting an fpu, an incorrect sequence of movw/movt was generated to construct a double literal. The test suite was hardwired to check these wrong values. The fault was caused by the explicit word swap in LowerConstantFP(). With -mbig-endian -mexecute-only -mfpu=none, a correct sequence of movw/movt is generated to construct a double literal. The test suite did not test this no fpu case. The test suite expected values have been corrected. The test file is updated to add testing of fpu=none case Reviewers: christof, llvm-commits, dmgreen Reviewed By: dmgreen Subscribers: dmgreen, kristof.beyls, hiraditya, danielkiss Tags: #llvm Differential Revision: https://reviews.llvm.org/D81259 Change-Id: Ia3737df243218c89c82f02b7f9f4032ecd5a3917 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 -- llvm/test/CodeGen/ARM/constantfp.ll | 29 ++++++++++++++++------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0bd726e..ee8fd65 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6644,8 +6644,6 @@ SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG, case MVT::f64: { SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32); SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32); - if (!ST->isLittle()) - std::swap(Lo, Hi); return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); } case MVT::f32: diff --git a/llvm/test/CodeGen/ARM/constantfp.ll b/llvm/test/CodeGen/ARM/constantfp.ll index d45d3dc..80bf74a 100644 --- a/llvm/test/CodeGen/ARM/constantfp.ll +++ b/llvm/test/CodeGen/ARM/constantfp.ll @@ -9,7 +9,10 @@ ; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s ; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m4 %s -o - \ -; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s +; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE --check-prefix=CHECK-XO-DOUBLE-BE-FPREGS %s + +; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m3 %s -o - \ +; RUN: | FileCheck --check-prefix=CHECK-XO-DOUBLE-BE %s ; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 -relocation-model=ropi %s -o - \ ; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s @@ -94,8 +97,8 @@ define arm_aapcs_vfpcc double @test_vmov_double_imm() { ; CHECK-XO-DOUBLE-NOT: vldr ; CHECK-XO-DOUBLE-BE-LABEL: test_vmov_double_imm: -; CHECK-XO-DOUBLE-BE: movs [[REG:r[0-9]+]], #0 -; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]] +; CHECK-XO-DOUBLE-BE-FPREGS: movs [[REG:r[0-9]+]], #0 +; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG]], [[REG]] ; CHECK-XO-DOUBLE-NOT: vldr ret double 0.0 } @@ -116,8 +119,8 @@ define arm_aapcs_vfpcc double @test_vmvn_double_imm() { ; CHECK-XO-DOUBLE-NOT: vldr ; CHECK-XO-DOUBLE-BE-LABEL: test_vmvn_double_imm: -; CHECK-XO-DOUBLE-BE: mvn [[REG:r[0-9]+]], #-1342177280 -; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]] +; CHECK-XO-DOUBLE-BE-FPREGS: mvn [[REG:r[0-9]+]], #-1342177280 +; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG]], [[REG]] ; CHECK-XO-DOUBLE-BE-NOT: vldr ret double 0x4fffffff4fffffff } @@ -141,9 +144,9 @@ define arm_aapcs_vfpcc double @test_notvmvn_double_imm() { ; CHECK-XO-DOUBLE-NOT: vldr ; CHECK-XO-DOUBLE-BE-LABEL: test_notvmvn_double_imm: -; CHECK-XO-DOUBLE-BE: mov.w [[REG1:r[0-9]+]], #-1 -; CHECK-XO-DOUBLE-BE: mvn [[REG2:r[0-9]+]], #-1342177280 -; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] +; CHECK-XO-DOUBLE-BE: mvn [[REG1:r[0-9]+]], #-1342177280 +; CHECK-XO-DOUBLE-BE: mov.w [[REG2:r[0-9]+]], #-1 +; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] ; CHECK-XO-DOUBLE-BE-NOT: vldr ret double 0x4fffffffffffffff } @@ -173,11 +176,11 @@ define arm_aapcs_vfpcc double @lower_const_f64_xo() { ; CHECK-XO-DOUBLE-NOT: vldr ; CHECK-XO-DOUBLE-BE-LABEL: lower_const_f64_xo -; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #27263 -; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #6291 -; CHECK-XO-DOUBLE-BE: movt [[REG1]], #29884 -; CHECK-XO-DOUBLE-BE: movt [[REG2]], #16340 -; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] +; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #6291 +; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #27263 +; CHECK-XO-DOUBLE-BE: movt [[REG1]], #16340 +; CHECK-XO-DOUBLE-BE: movt [[REG2]], #29884 +; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] ; CHECK-XO-DOUBLE-BE-NOT: vldr ret double 3.140000e-01 } -- 2.7.4