From 741b04b0b7912611a8a5b7e74462e87b8930a116 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 5 Nov 2020 15:44:49 -0800 Subject: [PATCH] [RISCV] Only enable GPR<->FPR32 bitconvert isel patterns on RV32. NFCI Bitconvert requires the bitwidth to match on both sides. On RV64 the GPR size is i64 so bitconvert between f32 isn't possible. The node should never be generated so the pattern won't ever match, but moving the patterns under IsRV32 makes it more obviously impossible. It also moves it to a similar location to the patterns for the custom nodes we use for RV64. --- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index c03d08d..d466069 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -303,10 +303,6 @@ def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; /// Float conversion operations -// Moves (no conversion) -def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>; -def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>; - // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so // are defined later. @@ -393,6 +389,9 @@ defm : StPat; } // Predicates = [HasStdExtF] let Predicates = [HasStdExtF, IsRV32] in { +def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>; +def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>; + // float->[u]int. Round-to-zero must be used. def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; -- 2.7.4