From 73ba3a1c64a4c5a1a4b87c773714814eecb84877 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 22 Jun 2016 11:15:55 +0200 Subject: [PATCH] ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate In order to be able to properly generate its pixel clock, the pll3-2x fixed factor needs to be able to change the PLL3 rate too. Add the needed extra compatible so that it behaves that way. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0840612..e374f4f 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -130,7 +130,7 @@ }; pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; + compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; clock-mult = <2>; -- 2.7.4