From 739be0f7659600b7d322263a653576d0a0c23f7e Mon Sep 17 00:00:00 2001 From: "keith.zhao" Date: Thu, 8 Sep 2022 15:07:41 +0800 Subject: [PATCH] riscv:linux:vout:mipi add 3 new mipi panel support Signed-off-by: keith --- drivers/gpu/drm/verisilicon/starfive_drm_dsi.c | 55 +- .../gpu/drm/verisilicon/starfive_drm_seeedpanel.c | 27 +- drivers/gpu/drm/verisilicon/vs_dc.c | 5 +- drivers/gpu/drm/verisilicon/vs_simple_enc.c | 11 +- drivers/phy/m31/7110-m31-dphy.h | 755 +++++++++++---------- drivers/phy/m31/phy-m31-dphy-tx0.c | 3 +- 6 files changed, 433 insertions(+), 423 deletions(-) mode change 100644 => 100755 drivers/gpu/drm/verisilicon/starfive_drm_dsi.c mode change 100644 => 100755 drivers/gpu/drm/verisilicon/starfive_drm_seeedpanel.c mode change 100644 => 100755 drivers/phy/m31/7110-m31-dphy.h mode change 100644 => 100755 drivers/phy/m31/phy-m31-dphy-tx0.c diff --git a/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c b/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c old mode 100644 new mode 100755 index 775b391..8e60ba6 --- a/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c +++ b/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c @@ -743,13 +743,13 @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, bpp, 0); dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check), bpp, DSI_HFP_FRAME_OVERHEAD); - //dpi to dsi transfer can not match , reconfig those parms + //dpi to dsi transfer can not match , reconfig those parms for waveshare + //for taobao old mipi panel .should change here : hsa 36 , hbp 108, hfp 288 if (mode->hdisplay == 800) { - dsi_cfg->hsa = 5; //19-14 - dsi_cfg->hbp = 5; //17-12 - dsi_cfg->hfp = 102; //108-6 + dsi_cfg->hsa = 117-DSI_HSA_FRAME_OVERHEAD; + dsi_cfg->hbp = 115-DSI_HBP_FRAME_OVERHEAD; + dsi_cfg->hfp = 209-DSI_HFP_FRAME_OVERHEAD; } - return 0; } @@ -791,14 +791,12 @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi, /* data rate in bytes/sec is not an integer, refuse the mode. */ dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal; - if (do_div(dlane_bps, lanes * dpi_htotal)) - return -EINVAL; - /* data rate was in bytes/sec, convert to bits/sec. */ - phy_cfg->hs_clk_rate = dlane_bps * 8; + phy_cfg->hs_clk_rate = 750000000; dsi_hfp_ext = adj_dsi_htotal - dsi_htotal; dsi_cfg->hfp += dsi_hfp_ext; + dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext; return 0; @@ -831,6 +829,8 @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi, if (ret) return ret; + phy_cfg->hs_clk_rate = 750000000; + dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD; @@ -961,26 +961,6 @@ static void cdns_dsi_bridge_disable(struct drm_bridge *bridge) cdns_dsi_clock_disable(dsi); } -#if 0 -static void release_txbyte_rst(void) -{ - void __iomem *regs = ioremap(0x12250000, 0x10000); - - u32 temp = readl(regs + SRST_ASSERT0); - - temp &= ~(0x1 << 18); - temp |= (0x0 & 0x1) << 18; - - writel(temp, regs + SRST_ASSERT0); - - do { - temp = readl(regs + SRST_STATUS0) >> 18; - temp &= 0x1; - } while (temp != 0x1); - //udelay(1); -} -#endif - static void cdns_dsi_hs_init(struct cdns_dsi *dsi) { struct cdns_dsi_output *output = &dsi->output; @@ -1093,20 +1073,11 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge) cdns_dsi_hs_init(dsi); cdns_dsi_init_link(dsi); - dsi_cfg.htotal=2544;//7110,0 while testing, must - writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa), dsi->regs + VID_HSIZE1); writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact), dsi->regs + VID_HSIZE2); - #if 0 - writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) | - VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay) | - VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start + 1), - dsi->regs + VID_VSIZE1); - #endif - writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end) | VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay - 1) | VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start), @@ -1137,17 +1108,11 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge) tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8, phy_cfg->hs_clk_rate); reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period; - //dev_info(dsi->base.dev, "tx_byte_period = %dns, reg_wakeup: 0x%08x\n", tx_byte_period, reg_wakeup); writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp), dsi->regs + VID_DPHY_TIME); -#if 0 - writel(0xafffb, dsi->regs + MCTL_DPHY_TIMEOUT1); - writel(0x3ffff, dsi->regs + MCTL_DPHY_TIMEOUT2); - writel(0x3ab05, dsi->regs + MCTL_ULPOUT_TIME); -#endif + vrefresh = drm_mode_vrefresh(mode);//display_timing_vrefresh(dpi); - vrefresh = 49;//display_timing_vrefresh(dpi); tmp = NSEC_PER_SEC / vrefresh; tmp /= tx_byte_period; for (div = 0; div <= CLK_DIV_MAX; div++) { diff --git a/drivers/gpu/drm/verisilicon/starfive_drm_seeedpanel.c b/drivers/gpu/drm/verisilicon/starfive_drm_seeedpanel.c old mode 100644 new mode 100755 index f6c39f5..e779d59 --- a/drivers/gpu/drm/verisilicon/starfive_drm_seeedpanel.c +++ b/drivers/gpu/drm/verisilicon/starfive_drm_seeedpanel.c @@ -219,16 +219,29 @@ static struct seeed_panel_dev *panel_to_seeed(struct drm_panel *panel) } static const struct drm_display_mode seeed_panel_modes[] = { +#ifdef PLL_1228M { - .clock = 20144262 / 1000, + .clock = 27306666 / 1000, .hdisplay = 800, - .hsync_start = 800 + 10, - .hsync_end = 800 + 10 + 5, - .htotal = 800 + 10 + 5 + 5, + .hsync_start = 800 + 93, + .hsync_end = 800 + 93 + 5, + .htotal = 800 + 93 + 5 + 5, .vdisplay = 480, - .vsync_start = 480 + 4, - .vsync_end = 480 + 4 + 5, - .vtotal = 480 + 4 + 5 + 5, + .vsync_start = 480 + 14, + .vsync_end = 480 + 14 + 5, + .vtotal = 480 + 14 + 5 + 5, + }, +#endif + {// pll 1188M + .clock = 29700000 / 1000, + .hdisplay = 800, + .hsync_start = 800 + 90, + .hsync_end = 800 + 90 + 5, + .htotal = 800 + 90 + 5 + 5, + .vdisplay = 480, + .vsync_start = 480 + 60, + .vsync_end = 480 + 60 + 5, + .vtotal = 480 + 60 + 5 + 5, }, }; diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index 1ae53ce..c1e88c4 100755 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -806,8 +806,9 @@ static void vs_dc_enable(struct device *dev, struct drm_crtc *crtc) display.enable = true; if (crtc_state->encoder_type == DRM_MODE_ENCODER_DSI){ - clk_set_rate(dc->dc8200_pix0, 20144263);//round up, 20144262+1 - clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0 );//child,parent + clk_set_rate(dc->dc8200_pix0, mode->clock*1000); + clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0); + udelay(1000); dc_hw_set_out(&dc->hw, OUT_DPI, display.id); }else{ clk_set_parent(dc->dc8200_clk_pix1, dc->hdmitx0_pixelclk); diff --git a/drivers/gpu/drm/verisilicon/vs_simple_enc.c b/drivers/gpu/drm/verisilicon/vs_simple_enc.c index f254ff3..11edc3c 100755 --- a/drivers/gpu/drm/verisilicon/vs_simple_enc.c +++ b/drivers/gpu/drm/verisilicon/vs_simple_enc.c @@ -216,22 +216,15 @@ static int encoder_bind(struct device *dev, struct device *master, void *data) drm_of_find_possible_crtcs(drm_dev, dev->of_node); encoder->possible_crtcs = 2; - /* output port is port1*/ - -#ifdef CONFIG_STARFIVE_DSI ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0,&tmp_panel, &bridge); if (ret){ - printk("==no panel, %d\n",ret); + printk("no panel, %d\n",ret); //dev_err_probe(dev, ret, "endpoint returns %d\n", ret); goto err; } if (tmp_panel) dev_err(dev, "found panel on endpoint\n"); -#else - ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL, &bridge); - if (ret) - goto err; -#endif + #if KERNEL_VERSION(5, 7, 0) <= LINUX_VERSION_CODE ret = drm_bridge_attach(encoder, bridge, NULL, 0); #else diff --git a/drivers/phy/m31/7110-m31-dphy.h b/drivers/phy/m31/7110-m31-dphy.h old mode 100644 new mode 100755 index 9ed496e..268bbc8 --- a/drivers/phy/m31/7110-m31-dphy.h +++ b/drivers/phy/m31/7110-m31-dphy.h @@ -1,359 +1,396 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -#ifndef __7110_M31_DPHY_H__ -#define __7110_M31_DPHY_H__ - -#define AON_POWER_READY_N_WIDTH 0x1U -#define AON_POWER_READY_N_SHIFT 0x0U -#define AON_POWER_READY_N_MASK 0x1U -#define CFG_CKLANE_SET_WIDTH 0x5U -#define CFG_CKLANE_SET_SHIFT 0x1U -#define CFG_CKLANE_SET_MASK 0x3EU -#define CFG_DATABUS16_SEL_WIDTH 0x1U -#define CFG_DATABUS16_SEL_SHIFT 0x6U -#define CFG_DATABUS16_SEL_MASK 0x40U -#define CFG_DPDN_SWAP_WIDTH 0x5U -#define CFG_DPDN_SWAP_SHIFT 0x7U -#define CFG_DPDN_SWAP_MASK 0xF80U -#define CFG_L0_SWAP_SEL_WIDTH 0x3U -#define CFG_L0_SWAP_SEL_SHIFT 0xCU -#define CFG_L0_SWAP_SEL_MASK 0x7000U -#define CFG_L1_SWAP_SEL_WIDTH 0x3U -#define CFG_L1_SWAP_SEL_SHIFT 0xFU -#define CFG_L1_SWAP_SEL_MASK 0x38000U -#define CFG_L2_SWAP_SEL_WIDTH 0x3U -#define CFG_L2_SWAP_SEL_SHIFT 0x12U -#define CFG_L2_SWAP_SEL_MASK 0x1C0000U -#define CFG_L3_SWAP_SEL_WIDTH 0x3U -#define CFG_L3_SWAP_SEL_SHIFT 0x15U -#define CFG_L3_SWAP_SEL_MASK 0xE00000U -#define CFG_L4_SWAP_SEL_WIDTH 0x3U -#define CFG_L4_SWAP_SEL_SHIFT 0x18U -#define CFG_L4_SWAP_SEL_MASK 0x7000000U -#define MPOSV_31_0__WIDTH 0x20U -#define MPOSV_31_0__SHIFT 0x0U -#define MPOSV_31_0__MASK 0xFFFFFFFFU -#define MPOSV_46_32__WIDTH 0xFU -#define MPOSV_46_32__SHIFT 0x0U -#define MPOSV_46_32__MASK 0x7FFFU -#define RGS_CDTX_PLL_FM_CPLT_WIDTH 0x1U -#define RGS_CDTX_PLL_FM_CPLT_SHIFT 0xFU -#define RGS_CDTX_PLL_FM_CPLT_MASK 0x8000U -#define RGS_CDTX_PLL_FM_OVER_WIDTH 0x1U -#define RGS_CDTX_PLL_FM_OVER_SHIFT 0x10U -#define RGS_CDTX_PLL_FM_OVER_MASK 0x10000U -#define RGS_CDTX_PLL_FM_UNDER_WIDTH 0x1U -#define RGS_CDTX_PLL_FM_UNDER_SHIFT 0x11U -#define RGS_CDTX_PLL_FM_UNDER_MASK 0x20000U -#define RGS_CDTX_PLL_UNLOCK_WIDTH 0x1U -#define RGS_CDTX_PLL_UNLOCK_SHIFT 0x12U -#define RGS_CDTX_PLL_UNLOCK_MASK 0x40000U -#define RG_CDTX_L0N_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L0N_HSTX_RES_SHIFT 0x13U -#define RG_CDTX_L0N_HSTX_RES_MASK 0xF80000U -#define RG_CDTX_L0P_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L0P_HSTX_RES_SHIFT 0x18U -#define RG_CDTX_L0P_HSTX_RES_MASK 0x1F000000U - -#define RG_CDTX_L1N_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L1N_HSTX_RES_SHIFT 0x0U -#define RG_CDTX_L1N_HSTX_RES_MASK 0x1FU -#define RG_CDTX_L1P_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L1P_HSTX_RES_SHIFT 0x5U -#define RG_CDTX_L1P_HSTX_RES_MASK 0x3E0U -#define RG_CDTX_L2N_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L2N_HSTX_RES_SHIFT 0xAU -#define RG_CDTX_L2N_HSTX_RES_MASK 0x7C00U -#define RG_CDTX_L2P_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L2P_HSTX_RES_SHIFT 0xFU -#define RG_CDTX_L2P_HSTX_RES_MASK 0xF8000U -#define RG_CDTX_L3N_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L3N_HSTX_RES_SHIFT 0x14U -#define RG_CDTX_L3N_HSTX_RES_MASK 0x1F00000U -#define RG_CDTX_L3P_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L3P_HSTX_RES_SHIFT 0x19U -#define RG_CDTX_L3P_HSTX_RES_MASK 0x3E000000U - -#define RG_CDTX_L4N_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L4N_HSTX_RES_SHIFT 0x0U -#define RG_CDTX_L4N_HSTX_RES_MASK 0x1FU -#define RG_CDTX_L4P_HSTX_RES_WIDTH 0x5U -#define RG_CDTX_L4P_HSTX_RES_SHIFT 0x5U -#define RG_CDTX_L4P_HSTX_RES_MASK 0x3E0U - -#define RG_CDTX_PLL_FBK_FRA_WIDTH 0x18U -#define RG_CDTX_PLL_FBK_FRA_SHIFT 0x0U -#define RG_CDTX_PLL_FBK_FRA_MASK 0xFFFFFFU - -#define RG_CDTX_PLL_FBK_INT_WIDTH 0x9U -#define RG_CDTX_PLL_FBK_INT_SHIFT 0x0U -#define RG_CDTX_PLL_FBK_INT_MASK 0x1FFU -#define RG_CDTX_PLL_FM_EN_WIDTH 0x1U -#define RG_CDTX_PLL_FM_EN_SHIFT 0x9U -#define RG_CDTX_PLL_FM_EN_MASK 0x200U -#define RG_CDTX_PLL_LDO_STB_X2_EN_WIDTH 0x1U -#define RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT 0xAU -#define RG_CDTX_PLL_LDO_STB_X2_EN_MASK 0x400U -#define RG_CDTX_PLL_PRE_DIV_WIDTH 0x2U -#define RG_CDTX_PLL_PRE_DIV_SHIFT 0xBU -#define RG_CDTX_PLL_PRE_DIV_MASK 0x1800U -#define RG_CDTX_PLL_SSC_DELTA_WIDTH 0x12U -#define RG_CDTX_PLL_SSC_DELTA_SHIFT 0xDU -#define RG_CDTX_PLL_SSC_DELTA_MASK 0x7FFFE000U - -#define RG_CDTX_PLL_SSC_DELTA_INIT_WIDTH 0x12U -#define RG_CDTX_PLL_SSC_DELTA_INIT_SHIFT 0x0U -#define RG_CDTX_PLL_SSC_DELTA_INIT_MASK 0x3FFFFU -#define RG_CDTX_PLL_SSC_EN_WIDTH 0x1U -#define RG_CDTX_PLL_SSC_EN_SHIFT 0x12U -#define RG_CDTX_PLL_SSC_EN_MASK 0x40000U -#define RG_CDTX_PLL_SSC_PRD_WIDTH 0xAU -#define RG_CDTX_PLL_SSC_PRD_SHIFT 0x13U -#define RG_CDTX_PLL_SSC_PRD_MASK 0x1FF80000U - -#define RG_CLANE_HS_CLK_POST_TIME_WIDTH 0x8U -#define RG_CLANE_HS_CLK_POST_TIME_SHIFT 0x0U -#define RG_CLANE_HS_CLK_POST_TIME_MASK 0xFFU -#define RG_CLANE_HS_CLK_PRE_TIME_WIDTH 0x8U -#define RG_CLANE_HS_CLK_PRE_TIME_SHIFT 0x8U -#define RG_CLANE_HS_CLK_PRE_TIME_MASK 0xFF00U -#define RG_CLANE_HS_PRE_TIME_WIDTH 0x8U -#define RG_CLANE_HS_PRE_TIME_SHIFT 0x10U -#define RG_CLANE_HS_PRE_TIME_MASK 0xFF0000U -#define RG_CLANE_HS_TRAIL_TIME_WIDTH 0x8U -#define RG_CLANE_HS_TRAIL_TIME_SHIFT 0x18U -#define RG_CLANE_HS_TRAIL_TIME_MASK 0xFF000000U - -#define RG_CLANE_HS_ZERO_TIME_WIDTH 0x8U -#define RG_CLANE_HS_ZERO_TIME_SHIFT 0x0U -#define RG_CLANE_HS_ZERO_TIME_MASK 0xFFU -#define RG_DLANE_HS_PRE_TIME_WIDTH 0x8U -#define RG_DLANE_HS_PRE_TIME_SHIFT 0x8U -#define RG_DLANE_HS_PRE_TIME_MASK 0xFF00U -#define RG_DLANE_HS_TRAIL_TIME_WIDTH 0x8U -#define RG_DLANE_HS_TRAIL_TIME_SHIFT 0x10U -#define RG_DLANE_HS_TRAIL_TIME_MASK 0xFF0000U -#define RG_DLANE_HS_ZERO_TIME_WIDTH 0x8U -#define RG_DLANE_HS_ZERO_TIME_SHIFT 0x18U -#define RG_DLANE_HS_ZERO_TIME_MASK 0xFF000000U - -#define RG_EXTD_CYCLE_SEL_WIDTH 0x3U -#define RG_EXTD_CYCLE_SEL_SHIFT 0x0U -#define RG_EXTD_CYCLE_SEL_MASK 0x7U - -#define SCFG_C_HS_PRE_ZERO_TIME_WIDTH 0x20U -#define SCFG_C_HS_PRE_ZERO_TIME_SHIFT 0x0U -#define SCFG_C_HS_PRE_ZERO_TIME_MASK 0xFFFFFFFFU - -#define SCFG_DPHY_SRC_SEL_WIDTH 0x1U -#define SCFG_DPHY_SRC_SEL_SHIFT 0x0U -#define SCFG_DPHY_SRC_SEL_MASK 0x1U -#define SCFG_DSI_TXREADY_ESC_SEL_WIDTH 0x2U -#define SCFG_DSI_TXREADY_ESC_SEL_SHIFT 0x1U -#define SCFG_DSI_TXREADY_ESC_SEL_MASK 0x6U -#define SCFG_PPI_C_READY_SEL_WIDTH 0x2U -#define SCFG_PPI_C_READY_SEL_SHIFT 0x3U -#define SCFG_PPI_C_READY_SEL_MASK 0x18U -#define VCONTROL_WIDTH 0x5U -#define VCONTROL_SHIFT 0x5U -#define VCONTROL_MASK 0x3E0U - -#define XCFGI_DW00_WIDTH 0x20U -#define XCFGI_DW00_SHIFT 0x0U -#define XCFGI_DW00_MASK 0xFFFFFFFFU - -#define XCFGI_DW01_WIDTH 0x20U -#define XCFGI_DW01_SHIFT 0x0U -#define XCFGI_DW01_MASK 0xFFFFFFFFU - -#define XCFGI_DW02_WIDTH 0x20U -#define XCFGI_DW02_SHIFT 0x0U -#define XCFGI_DW02_MASK 0xFFFFFFFFU - -#define XCFGI_DW03_WIDTH 0x20U -#define XCFGI_DW03_SHIFT 0x0U -#define XCFGI_DW03_MASK 0xFFFFFFFFU - -#define XCFGI_DW04_WIDTH 0x20U -#define XCFGI_DW04_SHIFT 0x0U -#define XCFGI_DW04_MASK 0xFFFFFFFFU - -#define XCFGI_DW05_WIDTH 0x20U -#define XCFGI_DW05_SHIFT 0x0U -#define XCFGI_DW05_MASK 0xFFFFFFFFU - -#define XCFGI_DW06_WIDTH 0x20U -#define XCFGI_DW06_SHIFT 0x0U -#define XCFGI_DW06_MASK 0xFFFFFFFFU - -#define XCFGI_DW07_WIDTH 0x20U -#define XCFGI_DW07_SHIFT 0x0U -#define XCFGI_DW07_MASK 0xFFFFFFFFU - -#define XCFGI_DW08_WIDTH 0x20U -#define XCFGI_DW08_SHIFT 0x0U -#define XCFGI_DW08_MASK 0xFFFFFFFFU - -#define XCFGI_DW09_WIDTH 0x20U -#define XCFGI_DW09_SHIFT 0x0U -#define XCFGI_DW09_MASK 0xFFFFFFFFU - -#define XCFGI_DW0A_WIDTH 0x20U -#define XCFGI_DW0A_SHIFT 0x0U -#define XCFGI_DW0A_MASK 0xFFFFFFFFU - -#define XCFGI_DW0B_WIDTH 0x20U -#define XCFGI_DW0B_SHIFT 0x0U -#define XCFGI_DW0B_MASK 0xFFFFFFFFU - -#define DBG1_MUX_DOUT_WIDTH 0x8U -#define DBG1_MUX_DOUT_SHIFT 0x0U -#define DBG1_MUX_DOUT_MASK 0xFFU -#define DBG1_MUX_SEL_WIDTH 0x5U -#define DBG1_MUX_SEL_SHIFT 0x8U -#define DBG1_MUX_SEL_MASK 0x1F00U -#define DBG2_MUX_DOUT_WIDTH 0x8U -#define DBG2_MUX_DOUT_SHIFT 0xDU -#define DBG2_MUX_DOUT_MASK 0x1FE000U -#define DBG2_MUX_SEL_WIDTH 0x5U -#define DBG2_MUX_SEL_SHIFT 0x15U -#define DBG2_MUX_SEL_MASK 0x3E00000U -#define REFCLK_IN_SEL_WIDTH 0x3U -#define REFCLK_IN_SEL_SHIFT 0x1AU -#define REFCLK_IN_SEL_MASK 0x1C000000U -#define RESETB_WIDTH 0x1U -#define RESETB_SHIFT 0x1DU -#define RESETB_MASK 0x20000000U - -//aonsys con -#define AON_GP_REG_WIDTH 0x20U -#define AON_GP_REG_SHIFT 0x0U -#define AON_GP_REG_MASK 0xFFFFFFFFU - - -#define M31_DPHY_REFCLK_RESERVED 0 -#define M31_DPHY_REFCLK_12M 1 -#define M31_DPHY_REFCLK_19_2M 2 -#define M31_DPHY_REFCLK_25M 3 -#define M31_DPHY_REFCLK_26M 4 -#define M31_DPHY_REFCLK_27M 5 -#define M31_DPHY_REFCLK_38_4M 6 -#define M31_DPHY_REFCLK_52M 7 -#define M31_DPHY_REFCLK_BUTT 8 - -#define DPHY_TX_PSW_EN_MASK (1<<30) - -struct m31_dphy_config { - int ref_clk; - unsigned long bitrate; - uint32_t pll_prev_div, pll_fbk_int, pll_fbk_fra, extd_cycle_sel; - uint32_t dlane_hs_pre_time, dlane_hs_zero_time, dlane_hs_trail_time; - uint32_t clane_hs_pre_time, clane_hs_zero_time, clane_hs_trail_time; - uint32_t clane_hs_clk_pre_time, clane_hs_clk_post_time; -}; - -#define M31_DPHY_REFCLK M31_DPHY_REFCLK_12M -#define M31_DPHY_BITRATE_ALIGN 10000000 - - - -static const struct m31_dphy_config m31_dphy_configs[] = { -#if (M31_DPHY_REFCLK == M31_DPHY_REFCLK_25M) - //25000000,M31_DPHY_HS_RATE_80M,0x1,0x66,0x666666,0x4,0x0E,0x1D,0x15,0x05,0x2B,0x0D,0x0F,0x71, //comment unusual config for simplicity - {25000000, 100000000, 0x1, 0x80, 0x000000, 0x4, 0x10, 0x21, 0x17, 0x07, 0x35, 0x0F, 0x0F, 0x73,}, - {25000000, 200000000, 0x1, 0x80, 0x000000, 0x3, 0x0C, 0x1B, 0x13, 0x07, 0x35, 0x0F, 0x07, 0x3F,}, - {25000000, 300000000, 0x1, 0xC0, 0x000000, 0x3, 0x11, 0x25, 0x19, 0x0A, 0x50, 0x15, 0x07, 0x45,}, - {25000000, 400000000, 0x1, 0x80, 0x000000, 0x2, 0x0A, 0x18, 0x11, 0x07, 0x35, 0x0F, 0x03, 0x25,}, - {25000000, 500000000, 0x1, 0xA0, 0x000000, 0x2, 0x0C, 0x1D, 0x14, 0x09, 0x42, 0x12, 0x03, 0x28,}, - {25000000, 600000000, 0x1, 0xC0, 0x000000, 0x2, 0x0E, 0x23, 0x17, 0x0A, 0x50, 0x15, 0x03, 0x2B,}, - {25000000, 700000000, 0x1, 0x70, 0x000000, 0x1, 0x08, 0x14, 0x0F, 0x06, 0x2F, 0x0E, 0x01, 0x16,}, - {25000000, 800000000, 0x1, 0x80, 0x000000, 0x1, 0x09, 0x17, 0x10, 0x07, 0x35, 0x0F, 0x01, 0x18,}, - {25000000, 900000000, 0x1, 0x90, 0x000000, 0x1, 0x0A, 0x19, 0x12, 0x08, 0x3C, 0x10, 0x01, 0x19,}, - {25000000, 1000000000, 0x1, 0xA0, 0x000000, 0x1, 0x0B, 0x1C, 0x13, 0x09, 0x42, 0x12, 0x01, 0x1B,}, - {25000000, 1100000000, 0x1, 0xB0, 0x000000, 0x1, 0x0C, 0x1E, 0x15, 0x09, 0x4A, 0x14, 0x01, 0x1D,}, - {25000000, 1200000000, 0x1, 0xC0, 0x000000, 0x1, 0x0E, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x01, 0x1E,}, - {25000000, 1300000000, 0x1, 0x68, 0x000000, 0x0, 0x07, 0x12, 0x0D, 0x05, 0x2C, 0x0D, 0x00, 0x0F,}, - {25000000, 1400000000, 0x1, 0x70, 0x000000, 0x0, 0x07, 0x14, 0x0E, 0x06, 0x2F, 0x0E, 0x00, 0x10,}, - {25000000, 1500000000, 0x1, 0x78, 0x000000, 0x0, 0x08, 0x14, 0x0F, 0x06, 0x32, 0x0E, 0x00, 0x11,}, - {25000000, 1600000000, 0x1, 0x80, 0x000000, 0x0, 0x09, 0x15, 0x10, 0x07, 0x35, 0x0F, 0x00, 0x12,}, - {25000000, 1700000000, 0x1, 0x88, 0x000000, 0x0, 0x09, 0x17, 0x10, 0x07, 0x39, 0x10, 0x00, 0x12,}, - {25000000, 1800000000, 0x1, 0x90, 0x000000, 0x0, 0x0A, 0x18, 0x11, 0x08, 0x3C, 0x10, 0x00, 0x13,}, - {25000000, 1900000000, 0x1, 0x98, 0x000000, 0x0, 0x0A, 0x1A, 0x12, 0x08, 0x3F, 0x11, 0x00, 0x14,}, - {25000000, 2000000000, 0x1, 0xA0, 0x000000, 0x0, 0x0B, 0x1B, 0x13, 0x09, 0x42, 0x12, 0x00, 0x15,}, - {25000000, 2100000000, 0x1, 0xA8, 0x000000, 0x0, 0x0B, 0x1C, 0x13, 0x09, 0x46, 0x13, 0x00, 0x15,}, - {25000000, 2200000000, 0x1, 0xB0, 0x000000, 0x0, 0x0C, 0x1D, 0x14, 0x09, 0x4A, 0x14, 0x00, 0x16,}, - {25000000, 2300000000, 0x1, 0xB8, 0x000000, 0x0, 0x0C, 0x1F, 0x15, 0x0A, 0x4C, 0x14, 0x00, 0x17,}, - {25000000, 2400000000, 0x1, 0xC0, 0x000000, 0x0, 0x0D, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x00, 0x18,}, - {25000000, 2500000000, 0x1, 0xC8, 0x000000, 0x0, 0x0E, 0x21, 0x16, 0x0B, 0x53, 0x16, 0x00, 0x18,}, -#elif (M31_DPHY_REFCLK == M31_DPHY_REFCLK_12M) - - {12000000, 180000000, 0x0, 0x78, 0x0 << 16 | 0x0<<8 | 0x0, 0x3, 0xb, 0x19, 0x12, 0x6, 0x30, 0xe, 0x7, 0x3e,}, - - {12000000, 500000000, 0x0, 0xa6, 0xaa << 16 | 0xaa << 8 | 0xaa, 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28,}, - {12000000, 510000000, 0x0, 0xaa, 0x0 << 16 | 0x0 << 8 | 0x0, 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28,}, - - {12000000, 590000000, 0x0, 0xc4, 0xaa << 16 | 0xaa << 8 | 0xaa, 0x2, 0xe, 0x22, 0x17, 0xa, 0x4f, 0x15, 0x3, 0x2b,}, - - {12000000, 690000000, 0x0, 0x73, 0x0 << 16 | 0x0 << 8 | 0x0, 0x1, 0x8, 0x14, 0xe, 0x6, 0x2e, 0xd, 0x1, 0x16,}, - - {12000000, 720000000, 0x0, 0x78, 0x0<<16 | 0x0 << 8 | 0x0, 0x1, 0x8, 0x15, 0xf, 0x6, 0x30, 0xe, 0x1, 0x17,}, - - {12000000, 840000000, 0x0, 0x8c, 0x0 << 16 | 0x0<<8 | 0x0, 0x1, 0x9, 0x18, 0x11, 0x7, 0x38, 0x10, 0x1, 0x19,}, - -#endif -}; - -static inline u32 sf_dphy_get_reg(void* io_addr, u32 shift, u32 mask) -{ - //void __iomem *io_addr = ioremap(addr, 0x10000); - u32 tmp; - tmp = readl(io_addr); - tmp = (tmp & mask) >> shift; - return tmp; -} - -static inline void sf_dphy_set_reg(void* io_addr, u32 data, u32 shift, u32 mask) -{ - //void __iomem *io_addr = ioremap(addr, 0x10000); - - u32 tmp; - tmp = readl(io_addr); - tmp &= ~mask; - tmp |= (data << shift) & mask; - writel(tmp, io_addr); -} - -static inline void sf_dphy_assert_rst(void* io_addr, u32 addr_status, u32 mask) -{ - //void __iomem *io_addr = ioremap(addr, 0x4); - - void __iomem *io_addr_status = ioremap(addr_status, 0x4); - - u32 tmp; - tmp = readl(io_addr); - tmp |= mask; - writel(tmp,io_addr); - do{ - tmp = readl(io_addr_status); - }while((tmp & mask)!=0); -} - -static inline void sf_dphy_clear_rst (void* io_addr, u32 addr_status, u32 mask) -{ - //void __iomem *io_addr = ioremap(addr, 0x4); - - void __iomem *io_addr_status = ioremap(addr_status, 0x4); - - u32 tmp; - tmp = readl(io_addr); - tmp &= ~mask; - writel(tmp, io_addr); - do{ - tmp = readl(io_addr_status); - }while((tmp & mask) != mask); -} - -#endif /* __7110_M31_DPHY_H__ */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __7110_M31_DPHY_H__ +#define __7110_M31_DPHY_H__ + +#define AON_POWER_READY_N_WIDTH 0x1U +#define AON_POWER_READY_N_SHIFT 0x0U +#define AON_POWER_READY_N_MASK 0x1U +#define CFG_CKLANE_SET_WIDTH 0x5U +#define CFG_CKLANE_SET_SHIFT 0x1U +#define CFG_CKLANE_SET_MASK 0x3EU +#define CFG_DATABUS16_SEL_WIDTH 0x1U +#define CFG_DATABUS16_SEL_SHIFT 0x6U +#define CFG_DATABUS16_SEL_MASK 0x40U +#define CFG_DPDN_SWAP_WIDTH 0x5U +#define CFG_DPDN_SWAP_SHIFT 0x7U +#define CFG_DPDN_SWAP_MASK 0xF80U +#define CFG_L0_SWAP_SEL_WIDTH 0x3U +#define CFG_L0_SWAP_SEL_SHIFT 0xCU +#define CFG_L0_SWAP_SEL_MASK 0x7000U +#define CFG_L1_SWAP_SEL_WIDTH 0x3U +#define CFG_L1_SWAP_SEL_SHIFT 0xFU +#define CFG_L1_SWAP_SEL_MASK 0x38000U +#define CFG_L2_SWAP_SEL_WIDTH 0x3U +#define CFG_L2_SWAP_SEL_SHIFT 0x12U +#define CFG_L2_SWAP_SEL_MASK 0x1C0000U +#define CFG_L3_SWAP_SEL_WIDTH 0x3U +#define CFG_L3_SWAP_SEL_SHIFT 0x15U +#define CFG_L3_SWAP_SEL_MASK 0xE00000U +#define CFG_L4_SWAP_SEL_WIDTH 0x3U +#define CFG_L4_SWAP_SEL_SHIFT 0x18U +#define CFG_L4_SWAP_SEL_MASK 0x7000000U +#define MPOSV_31_0__WIDTH 0x20U +#define MPOSV_31_0__SHIFT 0x0U +#define MPOSV_31_0__MASK 0xFFFFFFFFU +#define MPOSV_46_32__WIDTH 0xFU +#define MPOSV_46_32__SHIFT 0x0U +#define MPOSV_46_32__MASK 0x7FFFU +#define RGS_CDTX_PLL_FM_CPLT_WIDTH 0x1U +#define RGS_CDTX_PLL_FM_CPLT_SHIFT 0xFU +#define RGS_CDTX_PLL_FM_CPLT_MASK 0x8000U +#define RGS_CDTX_PLL_FM_OVER_WIDTH 0x1U +#define RGS_CDTX_PLL_FM_OVER_SHIFT 0x10U +#define RGS_CDTX_PLL_FM_OVER_MASK 0x10000U +#define RGS_CDTX_PLL_FM_UNDER_WIDTH 0x1U +#define RGS_CDTX_PLL_FM_UNDER_SHIFT 0x11U +#define RGS_CDTX_PLL_FM_UNDER_MASK 0x20000U +#define RGS_CDTX_PLL_UNLOCK_WIDTH 0x1U +#define RGS_CDTX_PLL_UNLOCK_SHIFT 0x12U +#define RGS_CDTX_PLL_UNLOCK_MASK 0x40000U +#define RG_CDTX_L0N_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L0N_HSTX_RES_SHIFT 0x13U +#define RG_CDTX_L0N_HSTX_RES_MASK 0xF80000U +#define RG_CDTX_L0P_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L0P_HSTX_RES_SHIFT 0x18U +#define RG_CDTX_L0P_HSTX_RES_MASK 0x1F000000U + +#define RG_CDTX_L1N_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L1N_HSTX_RES_SHIFT 0x0U +#define RG_CDTX_L1N_HSTX_RES_MASK 0x1FU +#define RG_CDTX_L1P_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L1P_HSTX_RES_SHIFT 0x5U +#define RG_CDTX_L1P_HSTX_RES_MASK 0x3E0U +#define RG_CDTX_L2N_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L2N_HSTX_RES_SHIFT 0xAU +#define RG_CDTX_L2N_HSTX_RES_MASK 0x7C00U +#define RG_CDTX_L2P_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L2P_HSTX_RES_SHIFT 0xFU +#define RG_CDTX_L2P_HSTX_RES_MASK 0xF8000U +#define RG_CDTX_L3N_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L3N_HSTX_RES_SHIFT 0x14U +#define RG_CDTX_L3N_HSTX_RES_MASK 0x1F00000U +#define RG_CDTX_L3P_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L3P_HSTX_RES_SHIFT 0x19U +#define RG_CDTX_L3P_HSTX_RES_MASK 0x3E000000U + +#define RG_CDTX_L4N_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L4N_HSTX_RES_SHIFT 0x0U +#define RG_CDTX_L4N_HSTX_RES_MASK 0x1FU +#define RG_CDTX_L4P_HSTX_RES_WIDTH 0x5U +#define RG_CDTX_L4P_HSTX_RES_SHIFT 0x5U +#define RG_CDTX_L4P_HSTX_RES_MASK 0x3E0U + +#define RG_CDTX_PLL_FBK_FRA_WIDTH 0x18U +#define RG_CDTX_PLL_FBK_FRA_SHIFT 0x0U +#define RG_CDTX_PLL_FBK_FRA_MASK 0xFFFFFFU + +#define RG_CDTX_PLL_FBK_INT_WIDTH 0x9U +#define RG_CDTX_PLL_FBK_INT_SHIFT 0x0U +#define RG_CDTX_PLL_FBK_INT_MASK 0x1FFU +#define RG_CDTX_PLL_FM_EN_WIDTH 0x1U +#define RG_CDTX_PLL_FM_EN_SHIFT 0x9U +#define RG_CDTX_PLL_FM_EN_MASK 0x200U +#define RG_CDTX_PLL_LDO_STB_X2_EN_WIDTH 0x1U +#define RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT 0xAU +#define RG_CDTX_PLL_LDO_STB_X2_EN_MASK 0x400U +#define RG_CDTX_PLL_PRE_DIV_WIDTH 0x2U +#define RG_CDTX_PLL_PRE_DIV_SHIFT 0xBU +#define RG_CDTX_PLL_PRE_DIV_MASK 0x1800U +#define RG_CDTX_PLL_SSC_DELTA_WIDTH 0x12U +#define RG_CDTX_PLL_SSC_DELTA_SHIFT 0xDU +#define RG_CDTX_PLL_SSC_DELTA_MASK 0x7FFFE000U + +#define RG_CDTX_PLL_SSC_DELTA_INIT_WIDTH 0x12U +#define RG_CDTX_PLL_SSC_DELTA_INIT_SHIFT 0x0U +#define RG_CDTX_PLL_SSC_DELTA_INIT_MASK 0x3FFFFU +#define RG_CDTX_PLL_SSC_EN_WIDTH 0x1U +#define RG_CDTX_PLL_SSC_EN_SHIFT 0x12U +#define RG_CDTX_PLL_SSC_EN_MASK 0x40000U +#define RG_CDTX_PLL_SSC_PRD_WIDTH 0xAU +#define RG_CDTX_PLL_SSC_PRD_SHIFT 0x13U +#define RG_CDTX_PLL_SSC_PRD_MASK 0x1FF80000U + +#define RG_CLANE_HS_CLK_POST_TIME_WIDTH 0x8U +#define RG_CLANE_HS_CLK_POST_TIME_SHIFT 0x0U +#define RG_CLANE_HS_CLK_POST_TIME_MASK 0xFFU +#define RG_CLANE_HS_CLK_PRE_TIME_WIDTH 0x8U +#define RG_CLANE_HS_CLK_PRE_TIME_SHIFT 0x8U +#define RG_CLANE_HS_CLK_PRE_TIME_MASK 0xFF00U +#define RG_CLANE_HS_PRE_TIME_WIDTH 0x8U +#define RG_CLANE_HS_PRE_TIME_SHIFT 0x10U +#define RG_CLANE_HS_PRE_TIME_MASK 0xFF0000U +#define RG_CLANE_HS_TRAIL_TIME_WIDTH 0x8U +#define RG_CLANE_HS_TRAIL_TIME_SHIFT 0x18U +#define RG_CLANE_HS_TRAIL_TIME_MASK 0xFF000000U + +#define RG_CLANE_HS_ZERO_TIME_WIDTH 0x8U +#define RG_CLANE_HS_ZERO_TIME_SHIFT 0x0U +#define RG_CLANE_HS_ZERO_TIME_MASK 0xFFU +#define RG_DLANE_HS_PRE_TIME_WIDTH 0x8U +#define RG_DLANE_HS_PRE_TIME_SHIFT 0x8U +#define RG_DLANE_HS_PRE_TIME_MASK 0xFF00U +#define RG_DLANE_HS_TRAIL_TIME_WIDTH 0x8U +#define RG_DLANE_HS_TRAIL_TIME_SHIFT 0x10U +#define RG_DLANE_HS_TRAIL_TIME_MASK 0xFF0000U +#define RG_DLANE_HS_ZERO_TIME_WIDTH 0x8U +#define RG_DLANE_HS_ZERO_TIME_SHIFT 0x18U +#define RG_DLANE_HS_ZERO_TIME_MASK 0xFF000000U + +#define RG_EXTD_CYCLE_SEL_WIDTH 0x3U +#define RG_EXTD_CYCLE_SEL_SHIFT 0x0U +#define RG_EXTD_CYCLE_SEL_MASK 0x7U + +#define SCFG_C_HS_PRE_ZERO_TIME_WIDTH 0x20U +#define SCFG_C_HS_PRE_ZERO_TIME_SHIFT 0x0U +#define SCFG_C_HS_PRE_ZERO_TIME_MASK 0xFFFFFFFFU + +#define SCFG_DPHY_SRC_SEL_WIDTH 0x1U +#define SCFG_DPHY_SRC_SEL_SHIFT 0x0U +#define SCFG_DPHY_SRC_SEL_MASK 0x1U +#define SCFG_DSI_TXREADY_ESC_SEL_WIDTH 0x2U +#define SCFG_DSI_TXREADY_ESC_SEL_SHIFT 0x1U +#define SCFG_DSI_TXREADY_ESC_SEL_MASK 0x6U +#define SCFG_PPI_C_READY_SEL_WIDTH 0x2U +#define SCFG_PPI_C_READY_SEL_SHIFT 0x3U +#define SCFG_PPI_C_READY_SEL_MASK 0x18U +#define VCONTROL_WIDTH 0x5U +#define VCONTROL_SHIFT 0x5U +#define VCONTROL_MASK 0x3E0U + +#define XCFGI_DW00_WIDTH 0x20U +#define XCFGI_DW00_SHIFT 0x0U +#define XCFGI_DW00_MASK 0xFFFFFFFFU + +#define XCFGI_DW01_WIDTH 0x20U +#define XCFGI_DW01_SHIFT 0x0U +#define XCFGI_DW01_MASK 0xFFFFFFFFU + +#define XCFGI_DW02_WIDTH 0x20U +#define XCFGI_DW02_SHIFT 0x0U +#define XCFGI_DW02_MASK 0xFFFFFFFFU + +#define XCFGI_DW03_WIDTH 0x20U +#define XCFGI_DW03_SHIFT 0x0U +#define XCFGI_DW03_MASK 0xFFFFFFFFU + +#define XCFGI_DW04_WIDTH 0x20U +#define XCFGI_DW04_SHIFT 0x0U +#define XCFGI_DW04_MASK 0xFFFFFFFFU + +#define XCFGI_DW05_WIDTH 0x20U +#define XCFGI_DW05_SHIFT 0x0U +#define XCFGI_DW05_MASK 0xFFFFFFFFU + +#define XCFGI_DW06_WIDTH 0x20U +#define XCFGI_DW06_SHIFT 0x0U +#define XCFGI_DW06_MASK 0xFFFFFFFFU + +#define XCFGI_DW07_WIDTH 0x20U +#define XCFGI_DW07_SHIFT 0x0U +#define XCFGI_DW07_MASK 0xFFFFFFFFU + +#define XCFGI_DW08_WIDTH 0x20U +#define XCFGI_DW08_SHIFT 0x0U +#define XCFGI_DW08_MASK 0xFFFFFFFFU + +#define XCFGI_DW09_WIDTH 0x20U +#define XCFGI_DW09_SHIFT 0x0U +#define XCFGI_DW09_MASK 0xFFFFFFFFU + +#define XCFGI_DW0A_WIDTH 0x20U +#define XCFGI_DW0A_SHIFT 0x0U +#define XCFGI_DW0A_MASK 0xFFFFFFFFU + +#define XCFGI_DW0B_WIDTH 0x20U +#define XCFGI_DW0B_SHIFT 0x0U +#define XCFGI_DW0B_MASK 0xFFFFFFFFU + +#define DBG1_MUX_DOUT_WIDTH 0x8U +#define DBG1_MUX_DOUT_SHIFT 0x0U +#define DBG1_MUX_DOUT_MASK 0xFFU +#define DBG1_MUX_SEL_WIDTH 0x5U +#define DBG1_MUX_SEL_SHIFT 0x8U +#define DBG1_MUX_SEL_MASK 0x1F00U +#define DBG2_MUX_DOUT_WIDTH 0x8U +#define DBG2_MUX_DOUT_SHIFT 0xDU +#define DBG2_MUX_DOUT_MASK 0x1FE000U +#define DBG2_MUX_SEL_WIDTH 0x5U +#define DBG2_MUX_SEL_SHIFT 0x15U +#define DBG2_MUX_SEL_MASK 0x3E00000U +#define REFCLK_IN_SEL_WIDTH 0x3U +#define REFCLK_IN_SEL_SHIFT 0x1AU +#define REFCLK_IN_SEL_MASK 0x1C000000U +#define RESETB_WIDTH 0x1U +#define RESETB_SHIFT 0x1DU +#define RESETB_MASK 0x20000000U + +//aonsys con +#define AON_GP_REG_WIDTH 0x20U +#define AON_GP_REG_SHIFT 0x0U +#define AON_GP_REG_MASK 0xFFFFFFFFU + + +#define M31_DPHY_REFCLK_RESERVED 0 +#define M31_DPHY_REFCLK_12M 1 +#define M31_DPHY_REFCLK_19_2M 2 +#define M31_DPHY_REFCLK_25M 3 +#define M31_DPHY_REFCLK_26M 4 +#define M31_DPHY_REFCLK_27M 5 +#define M31_DPHY_REFCLK_38_4M 6 +#define M31_DPHY_REFCLK_52M 7 +#define M31_DPHY_REFCLK_BUTT 8 + +#define DPHY_TX_PSW_EN_MASK (1<<30) + +struct m31_dphy_config { + int ref_clk; + unsigned long bitrate; + uint32_t pll_prev_div, pll_fbk_int, pll_fbk_fra, extd_cycle_sel; + uint32_t dlane_hs_pre_time, dlane_hs_zero_time, dlane_hs_trail_time; + uint32_t clane_hs_pre_time, clane_hs_zero_time, clane_hs_trail_time; + uint32_t clane_hs_clk_pre_time, clane_hs_clk_post_time; +}; + +#define M31_DPHY_REFCLK M31_DPHY_REFCLK_12M +#define M31_DPHY_BITRATE_ALIGN 10000000 + + + +static const struct m31_dphy_config m31_dphy_configs[] = { +#if (M31_DPHY_REFCLK == M31_DPHY_REFCLK_25M) + {25000000, 100000000, 0x1, 0x80, 0x000000, 0x4, 0x10, 0x21, 0x17, 0x07, 0x35, 0x0F, 0x0F, 0x73,}, + {25000000, 200000000, 0x1, 0x80, 0x000000, 0x3, 0x0C, 0x1B, 0x13, 0x07, 0x35, 0x0F, 0x07, 0x3F,}, + {25000000, 300000000, 0x1, 0xC0, 0x000000, 0x3, 0x11, 0x25, 0x19, 0x0A, 0x50, 0x15, 0x07, 0x45,}, + {25000000, 400000000, 0x1, 0x80, 0x000000, 0x2, 0x0A, 0x18, 0x11, 0x07, 0x35, 0x0F, 0x03, 0x25,}, + {25000000, 500000000, 0x1, 0xA0, 0x000000, 0x2, 0x0C, 0x1D, 0x14, 0x09, 0x42, 0x12, 0x03, 0x28,}, + {25000000, 600000000, 0x1, 0xC0, 0x000000, 0x2, 0x0E, 0x23, 0x17, 0x0A, 0x50, 0x15, 0x03, 0x2B,}, + {25000000, 700000000, 0x1, 0x70, 0x000000, 0x1, 0x08, 0x14, 0x0F, 0x06, 0x2F, 0x0E, 0x01, 0x16,}, + {25000000, 800000000, 0x1, 0x80, 0x000000, 0x1, 0x09, 0x17, 0x10, 0x07, 0x35, 0x0F, 0x01, 0x18,}, + {25000000, 900000000, 0x1, 0x90, 0x000000, 0x1, 0x0A, 0x19, 0x12, 0x08, 0x3C, 0x10, 0x01, 0x19,}, + {25000000, 1000000000, 0x1, 0xA0, 0x000000, 0x1, 0x0B, 0x1C, 0x13, 0x09, 0x42, 0x12, 0x01, 0x1B,}, + {25000000, 1100000000, 0x1, 0xB0, 0x000000, 0x1, 0x0C, 0x1E, 0x15, 0x09, 0x4A, 0x14, 0x01, 0x1D,}, + {25000000, 1200000000, 0x1, 0xC0, 0x000000, 0x1, 0x0E, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x01, 0x1E,}, + {25000000, 1300000000, 0x1, 0x68, 0x000000, 0x0, 0x07, 0x12, 0x0D, 0x05, 0x2C, 0x0D, 0x00, 0x0F,}, + {25000000, 1400000000, 0x1, 0x70, 0x000000, 0x0, 0x07, 0x14, 0x0E, 0x06, 0x2F, 0x0E, 0x00, 0x10,}, + {25000000, 1500000000, 0x1, 0x78, 0x000000, 0x0, 0x08, 0x14, 0x0F, 0x06, 0x32, 0x0E, 0x00, 0x11,}, + {25000000, 1600000000, 0x1, 0x80, 0x000000, 0x0, 0x09, 0x15, 0x10, 0x07, 0x35, 0x0F, 0x00, 0x12,}, + {25000000, 1700000000, 0x1, 0x88, 0x000000, 0x0, 0x09, 0x17, 0x10, 0x07, 0x39, 0x10, 0x00, 0x12,}, + {25000000, 1800000000, 0x1, 0x90, 0x000000, 0x0, 0x0A, 0x18, 0x11, 0x08, 0x3C, 0x10, 0x00, 0x13,}, + {25000000, 1900000000, 0x1, 0x98, 0x000000, 0x0, 0x0A, 0x1A, 0x12, 0x08, 0x3F, 0x11, 0x00, 0x14,}, + {25000000, 2000000000, 0x1, 0xA0, 0x000000, 0x0, 0x0B, 0x1B, 0x13, 0x09, 0x42, 0x12, 0x00, 0x15,}, + {25000000, 2100000000, 0x1, 0xA8, 0x000000, 0x0, 0x0B, 0x1C, 0x13, 0x09, 0x46, 0x13, 0x00, 0x15,}, + {25000000, 2200000000, 0x1, 0xB0, 0x000000, 0x0, 0x0C, 0x1D, 0x14, 0x09, 0x4A, 0x14, 0x00, 0x16,}, + {25000000, 2300000000, 0x1, 0xB8, 0x000000, 0x0, 0x0C, 0x1F, 0x15, 0x0A, 0x4C, 0x14, 0x00, 0x17,}, + {25000000, 2400000000, 0x1, 0xC0, 0x000000, 0x0, 0x0D, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x00, 0x18,}, + {25000000, 2500000000, 0x1, 0xC8, 0x000000, 0x0, 0x0E, 0x21, 0x16, 0x0B, 0x53, 0x16, 0x00, 0x18,}, +#elif (M31_DPHY_REFCLK == M31_DPHY_REFCLK_12M) + {12000000, 500000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28,}, + {12000000, 510000000, 0x0, 0xaa, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28,}, + {12000000, 520000000, 0x0, 0xad, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29,}, + {12000000, 530000000, 0x0, 0xb0, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x47, 0x13, 0x3, 0x29,}, + {12000000, 540000000, 0x0, 0xb4, 0x0<<16|0x0<<8|0x0, 0x2, 0xd, 0x1f, 0x15, 0x9, 0x48, 0x13, 0x3, 0x29,}, + {12000000, 550000000, 0x0, 0xb7, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x20, 0x16, 0x9, 0x4a, 0x14, 0x3, 0x2a,}, + {12000000, 560000000, 0x0, 0xba, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4a, 0x14, 0x3, 0x2a,}, + {12000000, 570000000, 0x0, 0xbe, 0x0<<16|0x0<<8|0x0, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4c, 0x14, 0x3, 0x2a,}, + {12000000, 580000000, 0x0, 0xc1, 0x55<<16|0x55<<8|0x55, 0x2, 0xe, 0x21, 0x16, 0xa, 0x4d, 0x14, 0x3, 0x2a,}, + {12000000, 590000000, 0x0, 0xc4, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xe, 0x22, 0x17, 0xa, 0x4f, 0x15, 0x3, 0x2b,}, + {12000000, 600000000, 0x0, 0xc8, 0x0<<16|0x0<<8|0x0, 0x2, 0xe, 0x23, 0x17, 0xa, 0x50, 0x15, 0x3, 0x2b,}, + {12000000, 610000000, 0x0, 0xcb, 0x55<<16|0x55<<8|0x55, 0x2, 0xf, 0x22, 0x17, 0xb, 0x50, 0x15, 0x3, 0x2b,}, + {12000000, 620000000, 0x0, 0xce, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xf, 0x23, 0x18, 0xb, 0x52, 0x16, 0x3, 0x2c,}, + {12000000, 630000000, 0x0, 0x69, 0x0<<16|0x0<<8|0x0, 0x1, 0x7, 0x12, 0xd, 0x5, 0x2a, 0xc, 0x1, 0x15,}, + {12000000, 640000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2b, 0xd, 0x1, 0x16,}, + {12000000, 650000000, 0x0, 0x6c, 0x55<<16|0x55<<8|0x55, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2c, 0xd, 0x1, 0x16,}, + {12000000, 660000000, 0x0, 0x6e, 0x0<<16|0x0<<8|0x0, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16,}, + {12000000, 670000000, 0x0, 0x6f, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16,}, + {12000000, 680000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x13, 0xe, 0x5, 0x2e, 0xd, 0x1, 0x16,}, + {12000000, 690000000, 0x0, 0x73, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x14, 0xe, 0x6, 0x2e, 0xd, 0x1, 0x16,}, + {12000000, 700000000, 0x0, 0x74, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x16,}, + {12000000, 710000000, 0x0, 0x76, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x17,}, + {12000000, 720000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x15, 0xf, 0x6, 0x30, 0xe, 0x1, 0x17,}, + {12000000, 730000000, 0x0, 0x79, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x15, 0xf, 0x6, 0x31, 0xe, 0x1, 0x17,}, + {12000000, 740000000, 0x0, 0x7b, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x15, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17,}, + {12000000, 750000000, 0x0, 0x7d, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x16, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17,}, + {12000000, 760000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x15, 0xf, 0x6, 0x33, 0xe, 0x1, 0x17,}, + {12000000, 770000000, 0x0, 0x80, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x15, 0x10, 0x6, 0x34, 0xf, 0x1, 0x18,}, + {12000000, 780000000, 0x0, 0x82, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x16, 0x10, 0x6, 0x35, 0xf, 0x1, 0x18,}, + {12000000, 790000000, 0x0, 0x83, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x16, 0x10, 0x7, 0x34, 0xf, 0x1, 0x18,}, + {12000000, 800000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x17, 0x10, 0x7, 0x35, 0xf, 0x1, 0x18,}, + {12000000, 810000000, 0x0, 0x87, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x17, 0x10, 0x7, 0x36, 0xf, 0x1, 0x18,}, + {12000000, 820000000, 0x0, 0x88, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x17, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18,}, + {12000000, 830000000, 0x0, 0x8a, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x18, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18,}, + {12000000, 840000000, 0x0, 0x8c, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x18, 0x11, 0x7, 0x38, 0x10, 0x1, 0x19,}, + {12000000, 850000000, 0x0, 0x8d, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x17, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19,}, + {12000000, 860000000, 0x0, 0x8f, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x18, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19,}, + {12000000, 870000000, 0x0, 0x91, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x18, 0x11, 0x7, 0x3a, 0x10, 0x1, 0x19,}, + {12000000, 880000000, 0x0, 0x92, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x18, 0x11, 0x7, 0x3b, 0x10, 0x1, 0x19,}, + {12000000, 890000000, 0x0, 0x94, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x19, 0x11, 0x7, 0x3c, 0x10, 0x1, 0x19,}, + {12000000, 900000000, 0x0, 0x96, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x10, 0x1, 0x19,}, + {12000000, 910000000, 0x0, 0x97, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x11, 0x1, 0x1a,}, + {12000000, 920000000, 0x0, 0x99, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3d, 0x11, 0x1, 0x1a,}, + {12000000, 930000000, 0x0, 0x9b, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a,}, + {12000000, 940000000, 0x0, 0x9c, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a,}, + {12000000, 950000000, 0x0, 0x9e, 0x55<<16|0x55<<8|0x55, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3f, 0x11, 0x1, 0x1a,}, + {12000000, 960000000, 0x0, 0xa0, 0x0<<16|0x0<<8|0x0, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x40, 0x11, 0x1, 0x1a,}, + {12000000, 970000000, 0x0, 0xa1, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x41, 0x12, 0x1, 0x1b,}, + {12000000, 980000000, 0x0, 0xa3, 0x55<<16|0x55<<8|0x55, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b,}, + {12000000, 990000000, 0x0, 0xa5, 0x0<<16|0x0<<8|0x0, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b,}, + {12000000, 1000000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1c, 0x13, 0x9, 0x42, 0x12, 0x1, 0x1b,}, + +#endif +}; + +static inline u32 sf_dphy_get_reg(void* io_addr, u32 shift, u32 mask) +{ + //void __iomem *io_addr = ioremap(addr, 0x10000); + u32 tmp; + tmp = readl(io_addr); + tmp = (tmp & mask) >> shift; + return tmp; +} + +static inline void sf_dphy_set_reg(void* io_addr, u32 data, u32 shift, u32 mask) +{ + //void __iomem *io_addr = ioremap(addr, 0x10000); + + u32 tmp; + tmp = readl(io_addr); + tmp &= ~mask; + tmp |= (data << shift) & mask; + writel(tmp, io_addr); +} + +static inline void sf_dphy_assert_rst(void* io_addr, u32 addr_status, u32 mask) +{ + //void __iomem *io_addr = ioremap(addr, 0x4); + + void __iomem *io_addr_status = ioremap(addr_status, 0x4); + + u32 tmp; + tmp = readl(io_addr); + tmp |= mask; + writel(tmp,io_addr); + do{ + tmp = readl(io_addr_status); + }while((tmp & mask)!=0); +} + +static inline void sf_dphy_clear_rst (void* io_addr, u32 addr_status, u32 mask) +{ + //void __iomem *io_addr = ioremap(addr, 0x4); + + void __iomem *io_addr_status = ioremap(addr_status, 0x4); + + u32 tmp; + tmp = readl(io_addr); + tmp &= ~mask; + writel(tmp, io_addr); + do{ + tmp = readl(io_addr_status); + }while((tmp & mask) != mask); +} + +#endif /* __7110_M31_DPHY_H__ */ diff --git a/drivers/phy/m31/phy-m31-dphy-tx0.c b/drivers/phy/m31/phy-m31-dphy-tx0.c old mode 100644 new mode 100755 index f36fbab..b043f95 --- a/drivers/phy/m31/phy-m31-dphy-tx0.c +++ b/drivers/phy/m31/phy-m31-dphy-tx0.c @@ -526,7 +526,8 @@ static int sys_m31_dphy_tx_configure(struct phy *phy, union phy_configure_opts * const struct m31_dphy_config *p; const uint32_t AON_POWER_READY_N_active = 0; dphy = phy_get_drvdata(phy); - bitrate = 500000000; + //bitrate = 680000000;//1228M 60fps + bitrate = 750000000;//1188M 60fps sf_dphy_set_reg(dphy->topsys + 0x8, 0x10, RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK); -- 2.7.4