From 73814050959ee5127328865e64c2faa5401daba2 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 9 May 2023 11:34:05 +0300 Subject: [PATCH] anv: fixup workaround 16011411144 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We're missing it for the memcpy with streamout Signed-off-by: Lionel Landwerlin Fixes: 5cc4075f95 ("anv, iris: Add Wa_16011411144 for DG2") Reviewed-by: José Roberto de Souza Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 4 ++-- src/intel/vulkan/genX_gpu_memcpy.c | 17 +++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 2499694..8a2dae5 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3344,7 +3344,7 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer) * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_* * state is not combined with other state changes. */ - if (intel_device_info_is_dg2(cmd_buffer->device->info)) { + if (intel_needs_workaround(cmd_buffer->device->info, 16011411144)) { anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_CS_STALL_BIT, "before SO_BUFFER change WA"); @@ -3378,7 +3378,7 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer) } } - if (intel_device_info_is_dg2(cmd_buffer->device->info)) { + if (intel_needs_workaround(cmd_buffer->device->info, 16011411144)) { /* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */ anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_CS_STALL_BIT, diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 19b97c2..b903ac9 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -167,6 +167,17 @@ emit_so_memcpy(struct anv_batch *batch, struct anv_device *device, }); + /* Wa_16011411144: + * + * SW must insert a PIPE_CONTROL cmd before and after the + * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_* + * state is not combined with other state changes. + */ + if (intel_needs_workaround(device->info, 16011411144)) { + anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) + pc.CommandStreamerStallEnable = true; + } + anv_batch_emit(batch, GENX(3DSTATE_SO_BUFFER), sob) { #if GFX_VER < 12 sob.SOBufferIndex = 0; @@ -189,6 +200,12 @@ emit_so_memcpy(struct anv_batch *batch, struct anv_device *device, sob.StreamOffset = 0; } + if (intel_needs_workaround(device->info, 16011411144)) { + /* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */ + anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) + pc.CommandStreamerStallEnable = true; + } + dw = anv_batch_emitn(batch, 5, GENX(3DSTATE_SO_DECL_LIST), .StreamtoBufferSelects0 = (1 << 0), .NumEntries0 = 1); -- 2.7.4