From 737bec38d0bd6ced5639169c1445791327911e01 Mon Sep 17 00:00:00 2001
From: Simon Atanasyan <simon@atanasyan.com>
Date: Wed, 7 Feb 2018 12:36:33 +0000
Subject: [PATCH] [mips] Handle 'M' and 'L' operand codes for memory operands

Both operand codes now work the same way in case of register or memory
operands. It print high-order or low-order word in a double-word
register or memory location.

llvm-svn: 324476
---
 llvm/lib/Target/Mips/MipsAsmPrinter.cpp  | 22 ++++++++++++++++------
 llvm/test/CodeGen/Mips/inlineasmmemop.ll | 22 +++++++++++++++++++++-
 2 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index f9de78dc281f..7953a36442d6 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -576,17 +576,27 @@ bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
   assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
   int Offset = OffsetMO.getImm();
 
-  // Currently we are expecting either no ExtraCode or 'D'
+  // Currently we are expecting either no ExtraCode or 'D','M','L'.
   if (ExtraCode) {
-    if (ExtraCode[0] == 'D')
+    switch (ExtraCode[0]) {
+    case 'D':
       Offset += 4;
-    else
+      break;
+    case 'M':
+      if (Subtarget->isLittle())
+        Offset += 4;
+      break;
+    case 'L':
+      if (!Subtarget->isLittle())
+        Offset += 4;
+      break;
+    default:
       return true; // Unknown modifier.
-    // FIXME: M = high order bits
-    // FIXME: L = low order bits
+    }
   }
 
-  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
+  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg())
+    << ")";
 
   return false;
 }
diff --git a/llvm/test/CodeGen/Mips/inlineasmmemop.ll b/llvm/test/CodeGen/Mips/inlineasmmemop.ll
index 61cbf93e667b..caf17f9dbf7d 100644
--- a/llvm/test/CodeGen/Mips/inlineasmmemop.ll
+++ b/llvm/test/CodeGen/Mips/inlineasmmemop.ll
@@ -1,4 +1,7 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -relocation-model=pic < %s \
+; RUN:   | FileCheck --check-prefixes=CHECK,EB %s
+; RUN: llc -march=mipsel -relocation-model=pic < %s \
+; RUN:   | FileCheck --check-prefixes=CHECK,EL %s
 
 ; Simple memory
 @g1 = external global i32
@@ -35,6 +38,18 @@ entry:
 ; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}})
 ; CHECK: #NO_APP
 
+; "M": High-order word of a double word.
+; CHECK: #APP
+; EB:    lw ${{[0-9]+}}, 12(${{[0-9]+}})
+; EL:    lw ${{[0-9]+}}, 16(${{[0-9]+}})
+; CHECK: #NO_APP
+
+; "L": Low-order word of a double word.
+; CHECK: #APP
+; EB:    lw ${{[0-9]+}}, 16(${{[0-9]+}})
+; EL:    lw ${{[0-9]+}}, 12(${{[0-9]+}})
+; CHECK: #NO_APP
+
 @b = common global [20 x i32] zeroinitializer, align 4
 
 define void @main() {
@@ -43,5 +58,10 @@ entry:
   tail call void asm sideeffect "    lw    $0, ${1:D}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
 ; First word. Notice, no 'D':
   tail call void asm sideeffect "    lw    $0, ${1}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+
+; High-order part.
+  tail call void asm sideeffect "    lw    $0, ${1:M}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+; Low-order part.
+  tail call void asm sideeffect "    lw    $0, ${1:L}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
   ret void
 }
-- 
2.34.1