From 72c81b94cb3aed05516a872c294899d304e27fc8 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Tue, 13 Aug 2019 06:55:32 +0000 Subject: [PATCH] [AArch64][GlobalISel] Replace explicit vreg creation with implicit using SrcOp. NFC. llvm-svn: 368653 --- llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 4df68fd..d19e0c1 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -2384,13 +2384,14 @@ bool AArch64InstructionSelector::selectTLSGlobalValue( MIB.buildInstr(AArch64::LOADgot, {AArch64::X0}, {}) .addGlobalAddress(&GV, 0, AArch64II::MO_TLS); - Register DestReg = MRI.createVirtualRegister(&AArch64::GPR64commonRegClass); - MIB.buildInstr(AArch64::LDRXui, {DestReg}, {Register(AArch64::X0)}).addImm(0); + auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass}, + {Register(AArch64::X0)}) + .addImm(0); // TLS calls preserve all registers except those that absolutely must be // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be // silly). - MIB.buildInstr(AArch64::BLR, {}, {DestReg}) + MIB.buildInstr(AArch64::BLR, {}, {Load}) .addDef(AArch64::X0, RegState::Implicit) .addRegMask(TRI.getTLSCallPreservedMask()); -- 2.7.4