From 7295512037e895eebfc689c72cd01acf7f358464 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 14 Jun 2019 10:21:56 +0200 Subject: [PATCH] radv: store the fast color clear values for each mip Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 38 +++++++++++++++++++++++++++----------- src/amd/vulkan/radv_meta_clear.c | 2 +- src/amd/vulkan/radv_private.h | 12 +++++++++++- 3 files changed, 39 insertions(+), 13 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index def60f7..cdc88f5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1687,23 +1687,27 @@ radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, static void radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t color_values[2]) { struct radeon_cmdbuf *cs = cmd_buffer->cs; - uint64_t va = radv_buffer_get_va(image->bo); - - va += image->offset + image->clear_value_offset; + uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel); + uint32_t level_count = radv_get_levelCount(image, range); + uint32_t count = 2 * level_count; assert(radv_image_has_cmask(image) || radv_image_has_dcc(image)); - radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating)); + radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating)); radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_PFP)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); - radeon_emit(cs, color_values[0]); - radeon_emit(cs, color_values[1]); + + for (uint32_t l = 0; l < level_count; l++) { + radeon_emit(cs, color_values[0]); + radeon_emit(cs, color_values[1]); + } } /** @@ -1711,13 +1715,22 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, */ void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, + const struct radv_image_view *iview, int cb_idx, uint32_t color_values[2]) { + struct radv_image *image = iview->image; + VkImageSubresourceRange range = { + .aspectMask = iview->aspect_mask, + .baseMipLevel = iview->base_mip, + .levelCount = iview->level_count, + .baseArrayLayer = iview->base_layer, + .layerCount = iview->layer_count, + }; + assert(radv_image_has_cmask(image) || radv_image_has_dcc(image)); - radv_set_color_clear_metadata(cmd_buffer, image, color_values); + radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values); radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx, color_values); @@ -4894,7 +4907,8 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, VkImageLayout src_layout, VkImageLayout dst_layout, unsigned src_queue_mask, - unsigned dst_queue_mask) + unsigned dst_queue_mask, + const VkImageSubresourceRange *range) { if (radv_image_has_cmask(image)) { uint32_t value = 0xffffffffu; /* Fully expanded mode. */ @@ -4929,7 +4943,8 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) { uint32_t color_values[2] = {}; - radv_set_color_clear_metadata(cmd_buffer, image, color_values); + radv_set_color_clear_metadata(cmd_buffer, image, range, + color_values); } } @@ -4947,7 +4962,8 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { radv_init_color_image_metadata(cmd_buffer, image, src_layout, dst_layout, - src_queue_mask, dst_queue_mask); + src_queue_mask, dst_queue_mask, + range); return; } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 44aaf92..c3678a7 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1549,7 +1549,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, *post_flush |= flush_bits; } - radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att, + radv_update_color_clear_metadata(cmd_buffer, iview, subpass_att, clear_color); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 37e56f0..3307551 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1174,6 +1174,7 @@ struct radv_cmd_buffer { }; struct radv_image; +struct radv_image_view; bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer); @@ -1251,7 +1252,7 @@ void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, VkImageAspectFlags aspects); void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, + const struct radv_image_view *iview, int cb_idx, uint32_t color_values[2]); @@ -1680,6 +1681,15 @@ radv_image_is_tc_compat_htile(const struct radv_image *image) return radv_image_has_htile(image) && image->tc_compatible_htile; } +static inline uint64_t +radv_image_get_fast_clear_va(const struct radv_image *image, + uint32_t base_level) +{ + uint64_t va = radv_buffer_get_va(image->bo); + va += image->offset + image->clear_value_offset + base_level * 8; + return va; +} + unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family); static inline uint32_t -- 2.7.4