From 725584e26d79d00ad4b14cab15babc4b4499d22e Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 15 Nov 2017 23:55:44 +0000 Subject: [PATCH] Add backend name to Target to enable runtime info to be fed back into TableGen Summary: Make it possible to feed runtime information back to tablegen to enable profile-guided tablegen-eration, detection of untested tablegen definitions, etc. Being a cross-compiler by nature, LLVM will potentially collect data for multiple architectures (e.g. when running 'ninja check'). We therefore need a way for TableGen to figure out what data applies to the backend it is generating at the time. This patch achieves that by including the name of the 'def X : Target ...' for the backend in the TargetRegistry. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev Differential Revision: https://reviews.llvm.org/D39742 llvm-svn: 318352 --- llvm/include/llvm/Support/TargetRegistry.h | 18 ++++++++++++++++-- llvm/lib/Support/TargetRegistry.cpp | 5 +++-- .../Target/AArch64/TargetInfo/AArch64TargetInfo.cpp | 6 +++--- llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp | 4 ++-- llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp | 8 ++++---- llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp | 9 +++++---- .../Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp | 4 ++-- llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp | 3 ++- llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp | 2 +- llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp | 8 ++++---- llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp | 4 ++-- .../Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp | 6 +++--- llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp | 10 +++++----- .../Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp | 4 ++-- llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp | 4 ++-- llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp | 3 ++- 16 files changed, 58 insertions(+), 40 deletions(-) diff --git a/llvm/include/llvm/Support/TargetRegistry.h b/llvm/include/llvm/Support/TargetRegistry.h index 21913d5..6e36d2f 100644 --- a/llvm/include/llvm/Support/TargetRegistry.h +++ b/llvm/include/llvm/Support/TargetRegistry.h @@ -187,6 +187,10 @@ private: /// ShortDesc - A short description of the target. const char *ShortDesc; + /// BackendName - The name of the backend implementation. This must match the + /// name of the 'def X : Target ...' in TableGen. + const char *BackendName; + /// HasJIT - Whether this target supports the JIT. bool HasJIT; @@ -279,6 +283,9 @@ public: /// getShortDescription - Get a short description of the target. const char *getShortDescription() const { return ShortDesc; } + /// getBackendName - Get the backend name. + const char *getBackendName() const { return BackendName; } + /// @} /// @name Feature Predicates /// @{ @@ -645,10 +652,15 @@ struct TargetRegistry { /// @param Name - The target name. This should be a static string. /// @param ShortDesc - A short target description. This should be a static /// string. + /// @param BackendName - The name of the backend. This should be a static + /// string that is the same for all targets that share a backend + /// implementation and must match the name used in the 'def X : Target ...' in + /// TableGen. /// @param ArchMatchFn - The arch match checking function for this target. /// @param HasJIT - Whether the target supports JIT code /// generation. static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc, + const char *BackendName, Target::ArchMatchFnTy ArchMatchFn, bool HasJIT = false); @@ -883,8 +895,10 @@ struct TargetRegistry { template struct RegisterTarget { - RegisterTarget(Target &T, const char *Name, const char *Desc) { - TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT); + RegisterTarget(Target &T, const char *Name, const char *Desc, + const char *BackendName) { + TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch, + HasJIT); } static bool getArchMatch(Triple::ArchType Arch) { diff --git a/llvm/lib/Support/TargetRegistry.cpp b/llvm/lib/Support/TargetRegistry.cpp index b5c2832..ed999fc 100644 --- a/llvm/lib/Support/TargetRegistry.cpp +++ b/llvm/lib/Support/TargetRegistry.cpp @@ -86,9 +86,9 @@ const Target *TargetRegistry::lookupTarget(const std::string &TT, return &*I; } -void TargetRegistry::RegisterTarget(Target &T, - const char *Name, +void TargetRegistry::RegisterTarget(Target &T, const char *Name, const char *ShortDesc, + const char *BackendName, Target::ArchMatchFnTy ArchMatchFn, bool HasJIT) { assert(Name && ShortDesc && ArchMatchFn && @@ -105,6 +105,7 @@ void TargetRegistry::RegisterTarget(Target &T, T.Name = Name; T.ShortDesc = ShortDesc; + T.BackendName = BackendName; T.ArchMatchFn = ArchMatchFn; T.HasJIT = HasJIT; } diff --git a/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp b/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp index 7ac9a5a..8fb1615 100644 --- a/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp +++ b/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp @@ -29,11 +29,11 @@ extern "C" void LLVMInitializeAArch64TargetInfo() { // Now register the "arm64" name for use with "-march". We don't want it to // take possession of the Triple::aarch64 tag though. TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64", - "ARM64 (little endian)", + "ARM64 (little endian)", "AArch64", [](Triple::ArchType) { return false; }, true); RegisterTarget Z( - getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)"); + getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64"); RegisterTarget W( - getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)"); + getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64"); } diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp index 92fb762..f61e2e4 100644 --- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp +++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp @@ -31,7 +31,7 @@ Target &llvm::getTheGCNTarget() { /// \brief Extern function to initialize the targets for the AMDGPU backend extern "C" void LLVMInitializeAMDGPUTargetInfo() { RegisterTarget R600(getTheAMDGPUTarget(), "r600", - "AMD GPUs HD2XXX-HD6XXX"); + "AMD GPUs HD2XXX-HD6XXX", "AMDGPU"); RegisterTarget GCN(getTheGCNTarget(), "amdgcn", - "AMD GCN GPUs"); + "AMD GCN GPUs", "AMDGPU"); } diff --git a/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp b/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp index caa69f8..b0491a4 100644 --- a/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp +++ b/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp @@ -30,12 +30,12 @@ Target &llvm::getTheThumbBETarget() { extern "C" void LLVMInitializeARMTargetInfo() { RegisterTarget X(getTheARMLETarget(), "arm", - "ARM"); + "ARM", "ARM"); RegisterTarget Y(getTheARMBETarget(), "armeb", - "ARM (big endian)"); + "ARM (big endian)", "ARM"); RegisterTarget A(getTheThumbLETarget(), - "thumb", "Thumb"); + "thumb", "Thumb", "ARM"); RegisterTarget B( - getTheThumbBETarget(), "thumbeb", "Thumb (big endian)"); + getTheThumbBETarget(), "thumbeb", "Thumb (big endian)", "ARM"); } diff --git a/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp b/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp index 265180b..1f7b8a0 100644 --- a/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp +++ b/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp @@ -28,9 +28,10 @@ Target &getTheBPFTarget() { extern "C" void LLVMInitializeBPFTargetInfo() { TargetRegistry::RegisterTarget(getTheBPFTarget(), "bpf", "BPF (host endian)", - [](Triple::ArchType) { return false; }, true); - RegisterTarget X(getTheBPFleTarget(), "bpfel", - "BPF (little endian)"); + "BPF", [](Triple::ArchType) { return false; }, + true); + RegisterTarget X( + getTheBPFleTarget(), "bpfel", "BPF (little endian)", "BPF"); RegisterTarget Y(getTheBPFbeTarget(), "bpfeb", - "BPF (big endian)"); + "BPF (big endian)", "BPF"); } diff --git a/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp b/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp index 0554646..a330f27 100644 --- a/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp +++ b/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp @@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() { } extern "C" void LLVMInitializeHexagonTargetInfo() { - RegisterTarget X(getTheHexagonTarget(), - "hexagon", "Hexagon"); + RegisterTarget X( + getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon"); } diff --git a/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp b/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp index e377db1..5eed0cb2 100644 --- a/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp +++ b/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp @@ -21,5 +21,6 @@ Target &getTheLanaiTarget() { } // namespace llvm extern "C" void LLVMInitializeLanaiTargetInfo() { - RegisterTarget X(getTheLanaiTarget(), "lanai", "Lanai"); + RegisterTarget X(getTheLanaiTarget(), "lanai", "Lanai", + "Lanai"); } diff --git a/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp b/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp index 62f52a1..dfa21f5 100644 --- a/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp +++ b/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp @@ -19,5 +19,5 @@ Target &llvm::getTheMSP430Target() { extern "C" void LLVMInitializeMSP430TargetInfo() { RegisterTarget X(getTheMSP430Target(), "msp430", - "MSP430 [experimental]"); + "MSP430 [experimental]", "MSP430"); } diff --git a/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp b/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp index 4c1edfa..ab494d5 100644 --- a/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp +++ b/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp @@ -32,17 +32,17 @@ Target &llvm::getTheMips64elTarget() { extern "C" void LLVMInitializeMipsTargetInfo() { RegisterTarget - X(getTheMipsTarget(), "mips", "Mips"); + X(getTheMipsTarget(), "mips", "Mips", "Mips"); RegisterTarget - Y(getTheMipselTarget(), "mipsel", "Mipsel"); + Y(getTheMipselTarget(), "mipsel", "Mipsel", "Mips"); RegisterTarget - A(getTheMips64Target(), "mips64", "Mips64 [experimental]"); + A(getTheMips64Target(), "mips64", "Mips64 [experimental]", "Mips"); RegisterTarget - B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]"); + B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]", "Mips"); } diff --git a/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp b/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp index d44876a..803d643 100644 --- a/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp +++ b/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp @@ -23,7 +23,7 @@ Target &llvm::getTheNVPTXTarget64() { extern "C" void LLVMInitializeNVPTXTargetInfo() { RegisterTarget X(getTheNVPTXTarget32(), "nvptx", - "NVIDIA PTX 32-bit"); + "NVIDIA PTX 32-bit", "NVPTX"); RegisterTarget Y(getTheNVPTXTarget64(), "nvptx64", - "NVIDIA PTX 64-bit"); + "NVIDIA PTX 64-bit", "NVPTX"); } diff --git a/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp b/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp index a637dd1..9795952 100644 --- a/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp +++ b/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp @@ -27,11 +27,11 @@ Target &llvm::getThePPC64LETarget() { extern "C" void LLVMInitializePowerPCTargetInfo() { RegisterTarget X(getThePPC32Target(), "ppc32", - "PowerPC 32"); + "PowerPC 32", "PPC"); RegisterTarget Y(getThePPC64Target(), "ppc64", - "PowerPC 64"); + "PowerPC 64", "PPC"); RegisterTarget Z( - getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE"); + getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE", "PPC"); } diff --git a/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp b/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp index 66178ac..d030bd9 100644 --- a/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp +++ b/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp @@ -27,9 +27,9 @@ Target &llvm::getTheSparcelTarget() { extern "C" void LLVMInitializeSparcTargetInfo() { RegisterTarget X(getTheSparcTarget(), "sparc", - "Sparc"); - RegisterTarget Y(getTheSparcV9Target(), - "sparcv9", "Sparc V9"); - RegisterTarget Z(getTheSparcelTarget(), - "sparcel", "Sparc LE"); + "Sparc", "Sparc"); + RegisterTarget Y( + getTheSparcV9Target(), "sparcv9", "Sparc V9", "Sparc"); + RegisterTarget Z( + getTheSparcelTarget(), "sparcel", "Sparc LE", "Sparc"); } diff --git a/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp b/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp index d3c53a4..e2b9efd 100644 --- a/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp +++ b/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp @@ -18,6 +18,6 @@ Target &llvm::getTheSystemZTarget() { } extern "C" void LLVMInitializeSystemZTargetInfo() { - RegisterTarget X(getTheSystemZTarget(), - "systemz", "SystemZ"); + RegisterTarget X( + getTheSystemZTarget(), "systemz", "SystemZ", "SystemZ"); } diff --git a/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp b/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp index d2654fc..16c2b56 100644 --- a/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp +++ b/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp @@ -22,8 +22,8 @@ Target &llvm::getTheX86_64Target() { extern "C" void LLVMInitializeX86TargetInfo() { RegisterTarget X( - getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above"); + getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above", "X86"); RegisterTarget Y( - getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64"); + getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64", "X86"); } diff --git a/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp b/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp index df5774c..41f4078 100644 --- a/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp +++ b/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp @@ -18,5 +18,6 @@ Target &llvm::getTheXCoreTarget() { } extern "C" void LLVMInitializeXCoreTargetInfo() { - RegisterTarget X(getTheXCoreTarget(), "xcore", "XCore"); + RegisterTarget X(getTheXCoreTarget(), "xcore", "XCore", + "XCore"); } -- 2.7.4