From 7244dc1e0651958b62222cafb15e34487851a6cd Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 3 Jun 2016 12:32:15 -0700 Subject: [PATCH] Revert "i965/fs: Allow scalar source regions on SNB math instructions." This reverts commit c1107cec44ab030c7fcc97c67baa12df1cc9d7b5. Apparently the hardware spec text I quoted in the commit message was outright lying about scalar source math being supported on SNB, the hardware seems to load 32 contiguous bits of data for each channel regardless of the regioning mode. Fixes regressions in the following CTS tests (which we didn't catch early due to CTS being temporarily disabled in our CI system): es2-cts.gtf.gl.atan.atan_vec3_frag_xvary es2-cts.gtf.gl.cos.cos_vec2_frag_xvary es2-cts.gtf.gl.atan.atan_vec2_frag_xvary es2-cts.gtf.gl.pow.pow_vec2_frag_xvary_yconsthalf es2-cts.gtf.gl.cos.cos_float_frag_xvary es2-cts.gtf.gl.pow.pow_float_frag_xvary_yconsthalf es2-cts.gtf.gl.atan.atan_vec3_frag_xvaryyvary es2-cts.gtf.gl.pow.pow_vec3_frag_xvary_yconsthalf es2-cts.gtf.gl.cos.cos_vec3_frag_xvary es2-cts.gtf.gl.atan.atan_vec2_frag_xvaryyvary Cc: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96346 Reported-by: Mark Janes Acked-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 ++---- src/mesa/drivers/dri/i965/brw_fs_builder.h | 10 ++++++++-- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 5 ++++- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 8218f9c..2a8e661 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2000,10 +2000,8 @@ void gen6_math(struct brw_codegen *p, assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1); if (devinfo->gen == 6) { - assert(has_scalar_region(src0) || - src0.hstride == BRW_HORIZONTAL_STRIDE_1); - assert(has_scalar_region(src1) || - src1.hstride == BRW_HORIZONTAL_STRIDE_1); + assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1); + assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1); } if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT || diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h b/src/mesa/drivers/dri/i965/brw_fs_builder.h index aef35f3..f22903e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_builder.h +++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h @@ -621,14 +621,20 @@ namespace brw { src_reg fix_math_operand(const src_reg &src) const { - /* Gen6 hardware ignores source modifiers (negate and abs) on math + /* Can't do hstride == 0 args on gen6 math, so expand it out. We + * might be able to do better by doing execsize = 1 math and then + * expanding that result out, but we would need to be careful with + * masking. + * + * Gen6 hardware ignores source modifiers (negate and abs) on math * instructions, so we also move to a temp to set those up. * * Gen7 relaxes most of the above restrictions, but still can't use IMM * operands to math */ if ((shader->devinfo->gen == 6 && - (src.file == IMM || src.abs || src.negate)) || + (src.file == IMM || src.file == UNIFORM || + src.abs || src.negate)) || (shader->devinfo->gen == 7 && src.file == IMM)) { const dst_reg tmp = vgrf(src.type); MOV(tmp, src); diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index 2a83eb9..438f681 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp @@ -578,9 +578,12 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) break; /* fallthrough */ case SHADER_OPCODE_POW: - /* Allow constant propagation into src1, and let constant combining + /* Allow constant propagation into src1 (except on Gen 6 which + * doesn't support scalar source math), and let constant combining * promote the constant on Gen < 8. */ + if (devinfo->gen == 6) + break; /* fallthrough */ case BRW_OPCODE_BFI1: case BRW_OPCODE_ASR: -- 2.7.4