From 72174a3eef230883444e7f7c77a89c4919bb38d5 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Sat, 19 Jun 2021 16:09:38 +0200 Subject: [PATCH] ac/nir: Update TCS output barriers with nir_var_mem_shared. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Output loads and stores are lowered to shared memory access, so we have to update the barriers to also reflect this. Closes: #4955 Fixes: bf966d1c1dd968116b8b547ca2739f5113caccb5 Signed-off-by: Timur Kristóf Reviewed-by: Daniel Schürmann Part-of: --- src/amd/common/ac_nir_lower_tess_io_to_mem.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index e9cd737..58d489e 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -430,6 +430,18 @@ lower_hs_output_load(nir_builder *b, .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); } +static void +update_hs_scoped_barrier(nir_intrinsic_instr *intrin) +{ + /* Output loads and stores are lowered to shared memory access, + * so we have to update the barriers to also reflect this. + */ + unsigned mem_modes = nir_intrinsic_memory_modes(intrin); + if (mem_modes & nir_var_shader_out) + mem_modes |= nir_var_mem_shared; + nir_intrinsic_set_memory_modes(intrin, mem_modes); +} + static nir_ssa_def * lower_hs_output_access(nir_builder *b, nir_instr *instr, @@ -442,8 +454,14 @@ lower_hs_output_access(nir_builder *b, intrin->intrinsic == nir_intrinsic_store_per_vertex_output) { lower_hs_output_store(b, intrin, st); return NIR_LOWER_INSTR_PROGRESS_REPLACE; - } else { + } else if (intrin->intrinsic == nir_intrinsic_load_output || + intrin->intrinsic == nir_intrinsic_load_per_vertex_output) { return lower_hs_output_load(b, intrin, st); + } else if (intrin->intrinsic == nir_intrinsic_scoped_barrier) { + update_hs_scoped_barrier(intrin); + return NIR_LOWER_INSTR_PROGRESS; + } else { + unreachable("intrinsic not supported by lower_hs_output_access"); } } @@ -571,7 +589,7 @@ lower_tes_input_load(nir_builder *b, } static bool -filter_any_output_access(const nir_instr *instr, +filter_hs_output_access(const nir_instr *instr, UNUSED const void *st) { if (instr->type != nir_instr_type_intrinsic) @@ -581,7 +599,8 @@ filter_any_output_access(const nir_instr *instr, return intrin->intrinsic == nir_intrinsic_store_output || intrin->intrinsic == nir_intrinsic_store_per_vertex_output || intrin->intrinsic == nir_intrinsic_load_output || - intrin->intrinsic == nir_intrinsic_load_per_vertex_output; + intrin->intrinsic == nir_intrinsic_load_per_vertex_output || + intrin->intrinsic == nir_intrinsic_scoped_barrier; } static bool @@ -658,7 +677,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, }; nir_shader_lower_instructions(shader, - filter_any_output_access, + filter_hs_output_access, lower_hs_output_access, &state); -- 2.7.4