From 71ffd49cc9b9da5d9e97b5153ee1fe33dfd61a43 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Thu, 4 Oct 2018 11:29:39 -0700 Subject: [PATCH] drm/i915/icl:Add Wa_1606682166 Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965 driver. Cc: Radhakrishna Sripada Signed-off-by: Anuj Phogat Reviewed-by: Mika Kuoppala Signed-off-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-6-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_workarounds.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c7e75f8..2078541 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7414,6 +7414,7 @@ enum { #define GEN7_SARCHKMD _MMIO(0xB000) #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) +#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) #define GEN7_L3SQCREG1 _MMIO(0xB010) #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index b298f53..e413659 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0)) I915_WRITE(GEN7_SARCHKMD, I915_READ(GEN7_SARCHKMD) | - GEN7_DISABLE_DEMAND_PREFETCH); + GEN7_DISABLE_DEMAND_PREFETCH | + GEN7_DISABLE_SAMPLER_PREFETCH); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) -- 2.7.4