From 71a474d563d912bbe83b5002343193090086d4cf Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Thu, 10 Aug 2017 09:52:55 +0000 Subject: [PATCH] [AArch64] Assembler support for v8.3 RCpc Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 llvm-svn: 310575 --- llvm/lib/Target/AArch64/AArch64.td | 5 ++++- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 12 ++++++++++ llvm/lib/Target/AArch64/AArch64InstrInfo.td | 10 +++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 2 ++ llvm/test/MC/AArch64/armv8.3a-rcpc.s | 23 +++++++++++++++++++ .../test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt | 26 ++++++++++++++++++++++ 6 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/AArch64/armv8.3a-rcpc.s create mode 100644 llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 7074fc5..4ef91f3 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -118,6 +118,9 @@ def FeatureDisableLatencySchedHeuristic : SubtargetFeature< "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", "Disable latency scheduling heuristic">; +def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", + "Enable support for RCPC extension">; + def FeatureUseRSqrt : SubtargetFeature< "use-reciprocal-square-root", "UseRSqrt", "true", "Use the reciprocal square root approximation">; @@ -147,7 +150,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", - "Support ARM v8.3a instructions", [HasV8_2aOps]>; + "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 0e50999..87352f6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1098,6 +1098,18 @@ class SpecialReturn opc, string asm> let Inst{9-5} = 0b11111; } +let mayLoad = 1 in +class RCPCLoad sz, string asm, RegisterClass RC> + : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>, + Sched<[]> { + bits<5> Rn; + bits<5> Rt; + let Inst{31-30} = sz; + let Inst{29-10} = 0b11100010111111110000; + let Inst{9-5} = Rn; + let Inst{4-0} = Rt; +} + //--- // Conditional branch instruction. //--- diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 37c35aa..31b6057 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -46,6 +46,8 @@ def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, "fuse-aes">; def HasSVE : Predicate<"Subtarget->hasSVE()">, AssemblerPredicate<"FeatureSVE", "sve">; +def HasRCPC : Predicate<"Subtarget->hasRCPC()">, + AssemblerPredicate<"FeatureRCPC", "rcpc">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; @@ -448,6 +450,14 @@ def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s", ".16b", ".4 def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">; } +let Predicates = [HasRCPC] in { + // v8.3 Release Consistent Processor Consistent support + def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>; + def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>; + def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>; + def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>; +} + def : InstAlias<"clrex", (CLREX 0xf)>; def : InstAlias<"isb", (ISB 0xf)>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 0ff3a90..d9b9909 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -73,6 +73,7 @@ protected: bool HasSPE = false; bool HasLSLFast = false; bool HasSVE = false; + bool HasRCPC = false; // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove = false; @@ -257,6 +258,7 @@ public: bool hasSPE() const { return HasSPE; } bool hasLSLFast() const { return HasLSLFast; } bool hasSVE() const { return HasSVE; } + bool hasRCPC() const { return HasRCPC; } bool isLittleEndian() const { return IsLittle; } diff --git a/llvm/test/MC/AArch64/armv8.3a-rcpc.s b/llvm/test/MC/AArch64/armv8.3a-rcpc.s new file mode 100644 index 0000000..c93e56e --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.3a-rcpc.s @@ -0,0 +1,23 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t + + ldaprb w0, [x0, #0] + ldaprh w0, [x17, #0] + ldapr w0, [x1, #0] + ldapr x0, [x0, #0] + ldapr w18, [x0] + ldapr x15, [x0] + +// CHECK: ldaprb w0, [x0] // encoding: [0x00,0xc0,0xbf,0x38] +// CHECK: ldaprh w0, [x17] // encoding: [0x20,0xc2,0xbf,0x78] +// CHECK: ldapr w0, [x1] // encoding: [0x20,0xc0,0xbf,0xb8] +// CHECK: ldapr x0, [x0] // encoding: [0x00,0xc0,0xbf,0xf8] +// CHECK: ldapr w18, [x0] // encoding: [0x12,0xc0,0xbf,0xb8] +// CHECK: ldapr x15, [x0] // encoding: [0x0f,0xc0,0xbf,0xf8] +// CHECK-REQ: error: invalid operand for instruction +// CHECK-REQ: error: invalid operand for instruction +// CHECK-REQ: error: invalid operand for instruction +// CHECK-REQ: error: invalid operand for instruction +// CHECK-REQ: error: instruction requires: rcpc +// CHECK-REQ: error: instruction requires: rcpc diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt new file mode 100644 index 0000000..99e3cb9 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt @@ -0,0 +1,26 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s + +# CHECK: ldaprb w0, [x0] +# CHECK: ldaprh w0, [x0] +# CHECK: ldapr w0, [x0] +# CHECK: ldapr x0, [x0] +[0x00,0xc0,0xbf,0x38] +[0x00,0xc0,0xbf,0x78] +[0x00,0xc0,0xbf,0xb8] +[0x00,0xc0,0xbf,0xf8] + +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s 2>&1 | FileCheck --check-prefix=CHECK-V8_2A %s + +# CHECK-V8_2A: warning: invalid instruction encoding +# CHECK-V8_2A: [0x00,0xc0,0xbf,0x38] +# CHECK-V8_2A: ^ +# CHECK-V8_2A: warning: invalid instruction encoding +# CHECK-V8_2A: [0x00,0xc0,0xbf,0x78] +# CHECK-V8_2A: ^ +# CHECK-V8_2A: warning: invalid instruction encoding +# CHECK-V8_2A: [0x00,0xc0,0xbf,0xb8] +# CHECK-V8_2A: ^ +# CHECK-V8_2A: warning: invalid instruction encoding +# CHECK-V8_2A: [0x00,0xc0,0xbf,0xf8] +# CHECK-V8_2A: ^ + -- 2.7.4