From 71919403dc86b40fafd9400738668f96679c551b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 2 Mar 2012 16:08:54 -0800 Subject: [PATCH] Revert "powerpc/usb: fix issue of CPU halt when missing USB PHY clock" This reverts commit 529febeee680dc22416fca033151a5e8bc620447. To quote Dirk: This commit introduces a check for the USB PHY clock. Problem is that CTRL_PHY_CLK_VALID bit seems not to be present on all Freescale ehci implementations, at least P1022 does not have it. So this check always fails and the driver never gets loaded. So we need to revert this patch. Reported-by: Dirk Eibach Cc: Shengzhou Liu Cc: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.c | 11 ++--------- drivers/usb/host/ehci-fsl.h | 1 - 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index c26a82e..b556a72 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); } -static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) +static void ehci_fsl_usb_setup(struct ehci_hcd *ehci) { struct usb_hcd *hcd = ehci_to_hcd(ehci); struct fsl_usb2_platform_data *pdata; @@ -299,19 +299,12 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) #endif out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); } - - if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) { - printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); - return -ENODEV; - } - return 0; } /* called after powerup, by probe or system-pm "wakeup" */ static int ehci_fsl_reinit(struct ehci_hcd *ehci) { - if (ehci_fsl_usb_setup(ehci)) - return -ENODEV; + ehci_fsl_usb_setup(ehci); ehci_port_power(ehci, 0); return 0; diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h index bdf43e2a..4918062 100644 --- a/drivers/usb/host/ehci-fsl.h +++ b/drivers/usb/host/ehci-fsl.h @@ -45,6 +45,5 @@ #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ -#define CTRL_PHY_CLK_VALID (1 << 17) #define SNOOP_SIZE_2GB 0x1e #endif /* _EHCI_FSL_H */ -- 2.7.4