From 7143224272aa1e0023c6f9e4621bf6eece38249b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 9 Apr 2019 23:30:36 +0000 Subject: [PATCH] [X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it. Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either. So we should ignore it in our disassembler. The missing instructions here were found by grepping the raw tablegen class definitions in the tablegen debug output. llvm-svn: 358040 --- llvm/lib/Target/X86/X86InstrAVX512.td | 42 +++++++++++++++++------------------ llvm/lib/Target/X86/X86InstrSSE.td | 37 +++++++++++++++--------------- 2 files changed, 40 insertions(+), 39 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index f7b9216..28661b5 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2055,7 +2055,7 @@ multiclass avx512_cmp_scalar, EVEX_4V, Sched<[sched]>; + imm:$cc)>, EVEX_4V, VEX_LIG, Sched<[sched]>; let mayLoad = 1 in defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, (outs _.KRC:$dst), @@ -2063,7 +2063,7 @@ multiclass avx512_cmp_scalar, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + imm:$cc)>, EVEX_4V, VEX_LIG, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[sched.Folded, sched.ReadAfterFold]>; defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, @@ -2074,7 +2074,7 @@ multiclass avx512_cmp_scalar, - EVEX_4V, EVEX_B, Sched<[sched]>; + EVEX_4V, VEX_LIG, EVEX_B, Sched<[sched]>; let isCodeGenOnly = 1 in { let isCommutable = 1 in @@ -2085,7 +2085,7 @@ multiclass avx512_cmp_scalar, - EVEX_4V, Sched<[sched]>; + EVEX_4V, VEX_LIG, Sched<[sched]>; def rm : AVX512Ii8<0xC2, MRMSrcMem, (outs _.KRC:$dst), (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$cc), @@ -2094,7 +2094,7 @@ multiclass avx512_cmp_scalar, - EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + EVEX_4V, VEX_LIG, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[sched.Folded, sched.ReadAfterFold]>; } } @@ -2674,10 +2674,10 @@ multiclass avx512_fp_fpclass_all opcVec, VecOpNode, sched, prd, "{q}">, EVEX_CD8<64, CD8VF> , VEX_W; defm SSZ : avx512_scalar_fpclass, + sched.Scl, f32x_info, prd>, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm SDZ : avx512_scalar_fpclass, + sched.Scl, f64x_info, prd>, VEX_LIG, EVEX_CD8<64, CD8VT1>, VEX_W; } @@ -5740,11 +5740,11 @@ multiclass avx512_fp_scalef_all opc, bits<8> opcScaler, string OpcodeStr defm SSZ : avx512_fp_scalef_scalar, avx512_fp_scalar_round, - EVEX_4V,EVEX_CD8<32, CD8VT1>; + EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm SDZ : avx512_fp_scalef_scalar, avx512_fp_scalar_round, - EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, VEX_W; // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { @@ -7365,7 +7365,7 @@ defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, XS, VEX_W, EVEX_CD8<64, CD8VT1>; defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, null_frag, WriteCvtI2SD, GR32, v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">, - XD, EVEX_CD8<32, CD8VT1>; + XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SD, GR64, v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">, @@ -7600,11 +7600,11 @@ let Predicates = [HasAVX512] in { def rr : AVX512, - EVEX, Sched<[sched]>; + EVEX, VEX_LIG, Sched<[sched]>; def rm : AVX512, - EVEX, Sched<[sched.Folded, sched.ReadAfterFold]>; + EVEX, VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold]>; } def rr_Int : AVX512, - EVEX,VEX_LIG , EVEX_B, Sched<[sched]>; + EVEX, VEX_LIG, EVEX_B, Sched<[sched]>; let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in def rm_Int : AVX512 opc, string OpcodeStr, SDNode OpNode, (ins _.RC:$src1, _.RC:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, - EVEX_4V, Sched<[sched]>; + EVEX_4V, VEX_LIG, Sched<[sched]>; defm rm : AVX512_maskable_scalar, EVEX_4V, + _.ScalarIntMemCPat:$src2)>, EVEX_4V, VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold]>; } } @@ -9059,9 +9059,9 @@ multiclass avx512_fp28_s opc, string OpcodeStr,X86VectorVTInfo _, multiclass avx512_eri_s opc, string OpcodeStr, SDNode OpNode, SDNode OpNodeSAE, X86FoldableSchedWrite sched> { defm SSZ : avx512_fp28_s, EVEX_CD8<32, CD8VT1>; + sched>, EVEX_CD8<32, CD8VT1>, VEX_LIG; defm SDZ : avx512_fp28_s, EVEX_CD8<64, CD8VT1>, VEX_W; + sched>, EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W; } let Predicates = [HasERI] in { @@ -9354,12 +9354,12 @@ multiclass avx512_rndscale_scalar opc, string OpcodeStr, defm VRNDSCALESSZ : avx512_rndscale_scalar<0x0A, "vrndscaless", SchedWriteFRnd.Scl, f32x_info>, - AVX512AIi8Base, EVEX_4V, + AVX512AIi8Base, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VRNDSCALESDZ : avx512_rndscale_scalar<0x0B, "vrndscalesd", SchedWriteFRnd.Scl, f64x_info>, - VEX_W, AVX512AIi8Base, EVEX_4V, + VEX_W, AVX512AIi8Base, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; multiclass avx512_masked_scalar, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, + []>, VEX_LIG, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, Sched<[SchedWriteFMA.Scl.Folded]>; defm V4FNMADDSSrm : AVX512_maskable_3src_in_asm<0xAB, MRMSrcMem, f32x_info, (outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3), "v4fnmaddss", "$src3, $src2", "$src2, $src3", - []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, + []>, VEX_LIG, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, Sched<[SchedWriteFMA.Scl.Folded]>; } diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index b7a6f4c..f2ce89b 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -1060,13 +1060,13 @@ defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v2f64, X86cvts2si, let isCodeGenOnly = 1 in { let Predicates = [UseAVX] in { defm VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, - i32mem, "cvtsi2ss{l}", WriteCvtI2SS, 0>, XS, VEX_4V; + i32mem, "cvtsi2ss{l}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_LIG; defm VCVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128, - i64mem, "cvtsi2ss{q}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_W; + i64mem, "cvtsi2ss{q}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_LIG, VEX_W; defm VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, - i32mem, "cvtsi2sd{l}", WriteCvtI2SD, 0>, XD, VEX_4V; + i32mem, "cvtsi2sd{l}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_LIG; defm VCVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128, - i64mem, "cvtsi2sd{q}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_W; + i64mem, "cvtsi2sd{q}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_LIG, VEX_W; } let Constraints = "$src1 = $dst" in { defm CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, @@ -1087,18 +1087,18 @@ let isCodeGenOnly = 1 in { let Predicates = [UseAVX] in { defm VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v4f32, X86cvtts2Int, ssmem, sse_load_f32, "cvttss2si", - WriteCvtSS2I>, XS, VEX; + WriteCvtSS2I>, XS, VEX, VEX_LIG; defm VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v4f32, X86cvtts2Int, ssmem, sse_load_f32, "cvttss2si", WriteCvtSS2I>, - XS, VEX, VEX_W; + XS, VEX, VEX_LIG, VEX_W; defm VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v2f64, X86cvtts2Int, sdmem, sse_load_f64, "cvttsd2si", - WriteCvtSS2I>, XD, VEX; + WriteCvtSS2I>, XD, VEX, VEX_LIG; defm VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v2f64, X86cvtts2Int, sdmem, sse_load_f64, "cvttsd2si", WriteCvtSS2I>, - XD, VEX, VEX_W; + XD, VEX, VEX_LIG, VEX_W; } defm CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v4f32, X86cvtts2Int, ssmem, sse_load_f32, "cvttss2si", @@ -1216,14 +1216,14 @@ def VCVTSD2SSrr_Int: I<0x5A, MRMSrcReg, "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4f32 (X86frounds VR128:$src1, (v2f64 VR128:$src2))))]>, - XD, VEX_4V, VEX_WIG, Requires<[UseAVX]>, + XD, VEX_4V, VEX_LIG, VEX_WIG, Requires<[UseAVX]>, Sched<[WriteCvtSD2SS]>; def VCVTSD2SSrm_Int: I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4f32 (X86frounds VR128:$src1, sse_load_f64:$src2)))]>, - XD, VEX_4V, VEX_WIG, Requires<[UseAVX]>, + XD, VEX_4V, VEX_LIG, VEX_WIG, Requires<[UseAVX]>, Sched<[WriteCvtSD2SS.Folded, WriteCvtSD2SS.ReadAfterFold]>; let Constraints = "$src1 = $dst" in { def CVTSD2SSrr_Int: I<0x5A, MRMSrcReg, @@ -1295,13 +1295,13 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in { def VCVTSS2SDrr_Int: I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, XS, VEX_4V, VEX_WIG, + []>, XS, VEX_4V, VEX_LIG, VEX_WIG, Requires<[HasAVX]>, Sched<[WriteCvtSS2SD]>; let mayLoad = 1 in def VCVTSS2SDrm_Int: I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, XS, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + []>, XS, VEX_4V, VEX_LIG, VEX_WIG, Requires<[HasAVX]>, Sched<[WriteCvtSS2SD.Folded, WriteCvtSS2SD.ReadAfterFold]>; let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix def CVTSS2SDrr_Int: I<0x5A, MRMSrcReg, @@ -1825,12 +1825,13 @@ let isCodeGenOnly = 1 in { let ExeDomain = SSEPackedSingle in defm VCMPSS : sse12_cmp_scalar_int, XS, VEX_4V; + SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, + XS, VEX_4V, VEX_LIG, VEX_WIG; let ExeDomain = SSEPackedDouble in defm VCMPSD : sse12_cmp_scalar_int, - XD, VEX_4V; + XD, VEX_4V, VEX_LIG, VEX_WIG; let Constraints = "$src1 = $dst" in { let ExeDomain = SSEPackedSingle in defm CMPSS : sse12_cmp_scalar_int, PS, VEX, VEX_WIG; + sse_load_f32, "ucomiss", WriteFCom>, PS, VEX, VEX_LIG, VEX_WIG; defm VUCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem, - sse_load_f64, "ucomisd", WriteFCom>, PD, VEX, VEX_WIG; + sse_load_f64, "ucomisd", WriteFCom>, PD, VEX, VEX_LIG, VEX_WIG; defm VCOMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem, - sse_load_f32, "comiss", WriteFCom>, PS, VEX, VEX_WIG; + sse_load_f32, "comiss", WriteFCom>, PS, VEX, VEX_LIG, VEX_WIG; defm VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem, - sse_load_f64, "comisd", WriteFCom>, PD, VEX, VEX_WIG; + sse_load_f64, "comisd", WriteFCom>, PD, VEX, VEX_LIG, VEX_WIG; } defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, "ucomiss", WriteFCom>, PS; -- 2.7.4