From 70f06dc60569414b653fb0cbd5ff1e4f58d254ce Mon Sep 17 00:00:00 2001 From: Bin Gao Date: Wed, 29 Feb 2012 10:45:25 -0800 Subject: [PATCH] intel_scu_ipc: Support 19.2M Hz crystal for CLV+ boards BZ: 25776 CLV A0 boards have 38.4M Hz crystal. Moving forward all CLV+ based boards will use 19.2M Hz crystal, the same frequency with MDFLD. To enable old CLV A0 boards, just enable CONFIG_CTP_CRYSTAL_38M4. For new CLV+ boards, simply disable CONFIG_CTP_CRYSTAL_38M4. Display, audio and camera are impacted from the crystal frequency change because they use oscillator output clocks from the Soc. Change-Id: I755a81c700f09a505b0a554b49be3ac07c7eb4f2 Signed-off-by: Bin Gao Reviewed-on: http://android.intel.com:8080/37049 Reviewed-by: Gross, Mark Reviewed-by: Mai, Leonard Reviewed-by: Pandit, Seema Tested-by: Wang, Zhifeng Reviewed-by: buildbot Tested-by: buildbot --- drivers/platform/x86/Kconfig | 14 ++++++++++++++ drivers/platform/x86/intel_scu_ipc.c | 9 +++++---- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 97a414d..e428893 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -653,6 +653,20 @@ config INTEL_SCU_IPC_UTIL low level access for debug work and updating the firmware. Say N unless you will be doing this on an Intel MID platform. +config CTP_CRYSTAL_38M4 + bool "38.4M Hz crystal for CLV A0 boards" + depends on INTEL_SCU_IPC + default n + ---help--- + Display, audio and camers use osillator output clocks from the + Soc. Currently SCU FW doesn't handle crystal frequency, thus + Linux kernel has to explicitly calculate the divider based on + the acutal crystal frequency, then SCU can correctly set up + the oscillator output clocks based on the divider. + Old CLV A0 boards use 38.4M crystal whereas CLV+ based boards + will use 19.2M crystal. Say y for CLV boards (ctp_pr0 build) + and n for CLV+ based boards (ctp_pr1 build) + config GPIO_INTEL_PMIC bool "Intel PMIC GPIO support" depends on INTEL_SCU_IPC && GPIOLIB diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c index 9fcbabc..a45ae22 100644 --- a/drivers/platform/x86/intel_scu_ipc.c +++ b/drivers/platform/x86/intel_scu_ipc.c @@ -2197,10 +2197,11 @@ int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz) ipc_wbuf[0] = clk; ipc_wbuf[1] = 0; if (khz) { - if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW) - base_freq = 38400; - else - base_freq = 19200; +#ifdef CONFIG_CTP_CRYSTAL_38M4 + base_freq = 38400; +#else + base_freq = 19200; +#endif div = base_freq / khz - 1; if (div >= 3 || (div + 1) * khz != base_freq) return -EINVAL; /* Allow only exact frequencies */ -- 2.7.4