From 70a7f137bc3a1583af569df9f76fce900d352807 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 5 Jan 2024 14:25:25 +0900 Subject: [PATCH] RISCV: configs: tizen_visionfive2: Enable CPU_FREQ config Enable CPU_FREQ configuration. It was missed during version updating. Change-Id: I6a2873886a51fb8dd3723c63c59648925a13ac9b Signed-off-by: Jaehoon Chung --- arch/riscv/configs/tizen_visionfive2_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 7a28e44..67532ce 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -28,6 +28,14 @@ CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_SOC_STARFIVE=y CONFIG_SMP=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -- 2.7.4