From 70583606b199d9ad6bb29347b9e1113c9495db3a Mon Sep 17 00:00:00 2001
From: Igor Breger <igor.breger@intel.com>
Date: Thu, 4 May 2017 07:34:58 +0000
Subject: [PATCH] [X86][AVX-512] Allow EVEX encoded instruction selection when
 available for mul v8i32.

Differential Revision: https://reviews.llvm.org/D32679

llvm-svn: 302127
---
 llvm/lib/Target/X86/X86InstrSSE.td      | 4 ++--
 llvm/test/CodeGen/X86/avx-isa-check.ll  | 5 +++++
 llvm/test/CodeGen/X86/avx512vl-arith.ll | 2 +-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 0ed2ab4..48da2fa 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6727,14 +6727,14 @@ let Predicates = [HasAVX] in
                                  loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
                                  VEX_4V, VEX_WIG;
 
-let Predicates = [HasAVX2] in {
+let Predicates = [HasAVX2, NoVLX] in
   defm VPMULLDY  : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
                                   loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
                                   VEX_4V, VEX_L, VEX_WIG;
+let Predicates = [HasAVX2] in
   defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
                                   loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
                                   VEX_4V, VEX_L, VEX_WIG;
-}
 
 let Constraints = "$src1 = $dst" in {
   defm PMULLD  : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
diff --git a/llvm/test/CodeGen/X86/avx-isa-check.ll b/llvm/test/CodeGen/X86/avx-isa-check.ll
index dffc807..5d66dfd 100644
--- a/llvm/test/CodeGen/X86/avx-isa-check.ll
+++ b/llvm/test/CodeGen/X86/avx-isa-check.ll
@@ -680,3 +680,8 @@ define   <4 x double> @_inreg4xdouble(double %a) {
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   ret <4 x double> %c
 }
+
+define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 {
+  %ret = mul <8 x i32> %arg1, %arg2
+  ret <8 x i32> %ret
+}
diff --git a/llvm/test/CodeGen/X86/avx512vl-arith.ll b/llvm/test/CodeGen/X86/avx512vl-arith.ll
index b7a7beb..9c056cd 100755
--- a/llvm/test/CodeGen/X86/avx512vl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-arith.ll
@@ -176,7 +176,7 @@ define <8 x i32> @vpsubd256_test(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
 define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) {
 ; CHECK-LABEL: vpmulld256_test:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
+; CHECK-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %x = mul <8 x i32> %i, %j
   ret <8 x i32> %x
-- 
2.7.4