From 6fd994b4b7acc292f34ea7da76193ca15521d4a6 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 8 Oct 2020 17:20:31 -0500 Subject: [PATCH] [Hexagon] Remove ISD node VSPLATW, use VSPLAT instead This is a step towards improving HVX codegen for splat. --- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 1 - llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 - llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 23 ++++++++++------------ llvm/lib/Target/Hexagon/HexagonPatternsHVX.td | 12 +---------- 4 files changed, 11 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 0e443c6..04abb21 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1851,7 +1851,6 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::PTRUE: return "HexagonISD::PTRUE"; case HexagonISD::PFALSE: return "HexagonISD::PFALSE"; case HexagonISD::VZERO: return "HexagonISD::VZERO"; - case HexagonISD::VSPLATW: return "HexagonISD::VSPLATW"; case HexagonISD::D2P: return "HexagonISD::D2P"; case HexagonISD::P2D: return "HexagonISD::P2D"; case HexagonISD::V2Q: return "HexagonISD::V2Q"; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index f41efd5..9d3d986 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -82,7 +82,6 @@ enum NodeType : unsigned { QTRUE, QFALSE, VZERO, - VSPLATW, // HVX splat of a 32-bit word with an arbitrary result type. TYPECAST, // No-op that's used to convert between different legal // types in a register. VALIGN, // Align two vectors (in Op0, Op1) to one that would have diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index ee200b3..85b6e6b 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -496,7 +496,9 @@ HexagonTargetLowering::buildHvxVectorReg(ArrayRef Values, auto *IdxN = dyn_cast(SplatV.getNode()); if (IdxN && IdxN->isNullValue()) return getZero(dl, VecTy, DAG); - return DAG.getNode(HexagonISD::VSPLATW, dl, VecTy, SplatV); + MVT WordTy = MVT::getVectorVT(MVT::i32, HwLen/4); + SDValue S = DAG.getNode(HexagonISD::VSPLAT, dl, WordTy, SplatV); + return DAG.getBitcast(VecTy, S); } // Delay recognizing constant vectors until here, so that we can generate @@ -1421,19 +1423,14 @@ HexagonTargetLowering::LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const { // Calculate the vectors of 1 and bitwidth(x). MVT ElemTy = ty(InpV).getVectorElementType(); unsigned ElemWidth = ElemTy.getSizeInBits(); - // Using uint64_t because a shift by 32 can happen. - uint64_t Splat1 = 0, SplatW = 0; - assert(isPowerOf2_32(ElemWidth) && ElemWidth <= 32); - for (unsigned i = 0; i != 32/ElemWidth; ++i) { - Splat1 = (Splat1 << ElemWidth) | 1; - SplatW = (SplatW << ElemWidth) | ElemWidth; - } - SDValue Vec1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, - DAG.getConstant(uint32_t(Splat1), dl, MVT::i32)); - SDValue VecW = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, - DAG.getConstant(uint32_t(SplatW), dl, MVT::i32)); - SDValue VecN1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, + + SDValue Vec1 = DAG.getNode(HexagonISD::VSPLAT, dl, ResTy, + DAG.getConstant(1, dl, MVT::i32)); + SDValue VecW = DAG.getNode(HexagonISD::VSPLAT, dl, ResTy, + DAG.getConstant(ElemWidth, dl, MVT::i32)); + SDValue VecN1 = DAG.getNode(HexagonISD::VSPLAT, dl, ResTy, DAG.getConstant(-1, dl, MVT::i32)); + // Do not use DAG.getNOT, because that would create BUILD_VECTOR with // a BITCAST. Here we can skip the BITCAST (so we don't have to handle // it separately in custom combine or selection). diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index c03e1c7..135c493 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -12,9 +12,6 @@ def SDTHexagonVINSERTW0: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>; -def SDTHexagonVSPLATW: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; -def HexagonVSPLATW: SDNode<"HexagonISD::VSPLATW", SDTHexagonVSPLATW>; - def HwLen2: SDNodeXForm(CurDAG->getSubtarget()); return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32); @@ -242,17 +239,10 @@ let Predicates = [UseHVX] in { def: Pat<(VecPI8 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrb $Rs))>; def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrh $Rs))>; def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrw $Rs))>; - - def: Pat<(VecI8 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>; - def: Pat<(VecI16 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>; - def: Pat<(VecI32 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>; - def: Pat<(VecPI8 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>; - def: Pat<(VecPI16 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>; - def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>; } class Vneg1 - : PatFrag<(ops), (VecTy (HexagonVSPLATW (i32 -1)))>; + : PatFrag<(ops), (VecTy (HexagonVSPLAT (i32 -1)))>; class Vnot : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1)>; -- 2.7.4