From 6fb990bef05e57b192a018cf28b6ac29b29c0c95 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Fri, 17 Jul 2015 13:32:45 +0900 Subject: [PATCH] fimc-is: Use proper type for CSIS register region pointer Aside of dropping the pointless TO_WORD_OFFSET() macro this let's us avoid errors on a 64-bit system where size of unsigned long is 8 bytes, as opposed to 4 bytes on 32-bit machines. Change-Id: Ibba3165211b1d0a11ea34918cf8fc7033718420e Signed-off-by: Sylwester Nawrocki --- .../exynos/fimc-is/fimc-is-device-csi.c | 11 ++-- .../exynos/fimc-is/fimc-is-device-csi.h | 8 ++- .../platform/exynos/fimc-is/fimc-is-hw-csi.c | 50 +++++++++---------- 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.c b/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.c index 23469ce287af..2e210825cf44 100644 --- a/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.c +++ b/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.c @@ -25,11 +25,6 @@ #include "fimc-is-device-csi.h" #include "fimc-is-device-sensor.h" #include "fimc-is-core.h" -extern void s5pcsis_enable_interrupts(unsigned long __iomem *base_reg, struct fimc_is_image *image, bool on); -extern void s5pcsis_set_hsync_settle(unsigned long __iomem *base_reg, int settle); -extern void s5pcsis_set_params(unsigned long __iomem *base_reg, struct fimc_is_image *image, u32 lanes); -extern void s5pcsis_reset(unsigned long __iomem *base_reg); -extern void s5pcsis_system_enable(unsigned long __iomem *base_reg, int on, u32 lanes); static u32 get_hsync_settle(struct fimc_is_sensor_cfg *cfg, const u32 cfgs, u32 width, u32 height, u32 framerate) { @@ -180,7 +175,7 @@ static int csi_stream_on(struct fimc_is_device_csi *csi) { int ret = 0; u32 settle; - unsigned long __iomem *base_reg; + void __iomem *base_reg; BUG_ON(!csi); BUG_ON(!csi->sensor_cfg); @@ -215,7 +210,7 @@ static int csi_stream_on(struct fimc_is_device_csi *csi) static int csi_stream_off(struct fimc_is_device_csi *csi) { int ret = 0; - unsigned long __iomem *base_reg; + void __iomem *base_reg; BUG_ON(!csi); @@ -223,7 +218,7 @@ static int csi_stream_off(struct fimc_is_device_csi *csi) s5pcsis_enable_interrupts(base_reg, &csi->image, false); /* lane total count = csi->lanes + 1 (CSI_DATA_LANES_1 is 0) */ - s5pcsis_system_enable(base_reg, false, (csi->lanes + 1)); + s5pcsis_system_enable(base_reg, false, csi->lanes + 1); return ret; } diff --git a/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.h b/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.h index 9f90d5ce9f34..dfde9ac042c8 100644 --- a/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.h +++ b/drivers/media/platform/exynos/fimc-is/fimc-is-device-csi.h @@ -8,7 +8,7 @@ struct fimc_is_device_csi { /* channel information */ u32 instance; - unsigned long __iomem *base_reg; + void __iomem *base_reg; struct phy *phy; /* for settle time */ @@ -29,4 +29,10 @@ int __must_check fimc_is_csi_probe(void *parent, u32 instance); int __must_check fimc_is_csi_open(struct v4l2_subdev *subdev); int __must_check fimc_is_csi_close(struct v4l2_subdev *subdev); +void s5pcsis_enable_interrupts(void __iomem *base_reg, struct fimc_is_image *image, bool on); +void s5pcsis_set_hsync_settle(void __iomem *base_reg, int settle); +void s5pcsis_set_params(void __iomem *base_reg, struct fimc_is_image *image, u32 lanes); +void s5pcsis_reset(void __iomem *base_reg); +void s5pcsis_system_enable(void __iomem *base_reg, int on, u32 lanes); + #endif diff --git a/drivers/media/platform/exynos/fimc-is/fimc-is-hw-csi.c b/drivers/media/platform/exynos/fimc-is/fimc-is-hw-csi.c index d24522beb9a0..07257f44045c 100644 --- a/drivers/media/platform/exynos/fimc-is/fimc-is-hw-csi.c +++ b/drivers/media/platform/exynos/fimc-is/fimc-is-hw-csi.c @@ -116,10 +116,10 @@ #define CSIS_MAX_PIX_WIDTH (0xffff) #define CSIS_MAX_PIX_HEIGHT (0xffff) -void s5pcsis_enable_interrupts(unsigned long __iomem *base_reg, +void s5pcsis_enable_interrupts(void __iomem *base_reg, struct fimc_is_image *image, bool on) { - u32 val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_INTMSK)); + u32 val = readl(base_reg + S5PCSIS_INTMSK); val = on ? val | S5PCSIS_INTMSK_EN_ALL : val & ~S5PCSIS_INTMSK_EN_ALL; @@ -134,22 +134,22 @@ void s5pcsis_enable_interrupts(unsigned long __iomem *base_reg, } } - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_INTMSK)); + writel(val, base_reg + S5PCSIS_INTMSK); } -void s5pcsis_reset(unsigned long __iomem *base_reg) +void s5pcsis_reset(void __iomem *base_reg) { - u32 val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + u32 val = readl(base_reg + S5PCSIS_CTRL); - writel(val | S5PCSIS_CTRL_RESET, base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + writel(val | S5PCSIS_CTRL_RESET, base_reg + S5PCSIS_CTRL); udelay(10); } -void s5pcsis_system_enable(unsigned long __iomem *base_reg, int on, u32 lanes) +void s5pcsis_system_enable(void __iomem *base_reg, int on, u32 lanes) { u32 val; - val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + val = readl(base_reg + S5PCSIS_CTRL); val |= S5PCSIS_CTRL_WCLK_EXTCLK; @@ -158,18 +158,18 @@ void s5pcsis_system_enable(unsigned long __iomem *base_reg, int on, u32 lanes) val |= S5PCSIS_CTRL_WCLK_EXTCLK; } else val &= ~S5PCSIS_CTRL_ENABLE; - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + writel(val, base_reg + S5PCSIS_CTRL); - val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_DPHYCTRL)); + val = readl(base_reg + S5PCSIS_DPHYCTRL); if (on) val |= S5PCSIS_DPHYCTRL_DPHY_ON(lanes); else val &= ~S5PCSIS_DPHYCTRL_DPHY_ON(lanes); - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_DPHYCTRL)); + writel(val, base_reg + S5PCSIS_DPHYCTRL); } /* Called with the state.lock mutex held */ -static void __s5pcsis_set_format(unsigned long __iomem *base_reg, +static void __s5pcsis_set_format(void __iomem *base_reg, struct fimc_is_image *image) { u32 val; @@ -177,7 +177,7 @@ static void __s5pcsis_set_format(unsigned long __iomem *base_reg, BUG_ON(!image); /* Color format */ - val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_CONFIG)); + val = readl(base_reg + S5PCSIS_CONFIG); if (image->format.pixelformat == V4L2_PIX_FMT_SGRBG8) val = (val & ~S5PCSIS_CFG_FMT_MASK) | S5PCSIS_CFG_FMT_RAW8; @@ -185,39 +185,39 @@ static void __s5pcsis_set_format(unsigned long __iomem *base_reg, val = (val & ~S5PCSIS_CFG_FMT_MASK) | S5PCSIS_CFG_FMT_RAW10; val |= S5PCSIS_CFG_END_INTERVAL(1); - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_CONFIG)); + writel(val, base_reg + S5PCSIS_CONFIG); /* Pixel resolution */ val = (image->window.o_width << 16) | image->window.o_height; - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_RESOL)); + writel(val, base_reg + S5PCSIS_RESOL); /* Output channel2 for DT */ if (image->format.field == V4L2_FIELD_INTERLACED) { - val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_CONFIG_CH2)); + val = readl(base_reg + S5PCSIS_CONFIG_CH2); val |= S5PCSIS_CFG_VIRTUAL_CH(2); val |= S5PCSIS_CFG_END_INTERVAL(1); val = (val & ~S5PCSIS_CFG_FMT_MASK) | S5PCSIS_CFG_FMT_USER(1); - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_CONFIG_CH2)); + writel(val, base_reg + S5PCSIS_CONFIG_CH2); } } -void s5pcsis_set_hsync_settle(unsigned long __iomem *base_reg, u32 settle) +void s5pcsis_set_hsync_settle(void __iomem *base_reg, u32 settle) { - u32 val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_DPHYCTRL)); + u32 val = readl(base_reg + (S5PCSIS_DPHYCTRL)); val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 24); - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_DPHYCTRL)); + writel(val, base_reg + S5PCSIS_DPHYCTRL); } -void s5pcsis_set_params(unsigned long __iomem *base_reg, +void s5pcsis_set_params(void __iomem *base_reg, struct fimc_is_image *image, u32 lanes) { u32 val; __s5pcsis_set_format(base_reg, image); - val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + val = readl(base_reg + S5PCSIS_CTRL); val &= ~S5PCSIS_CTRL_ALIGN_32BIT; val |= S5PCSIS_CTRL_NUMOFDATALANE(lanes); @@ -232,9 +232,9 @@ void s5pcsis_set_params(unsigned long __iomem *base_reg, /* Not using external clock. */ val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; - writel(val, base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + writel(val, base_reg + S5PCSIS_CTRL); /* Update the shadow register. */ - val = readl(base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); - writel(val | S5PCSIS_CTRL_UPDATE_SHADOW(0), base_reg + TO_WORD_OFFSET(S5PCSIS_CTRL)); + val = readl(base_reg + S5PCSIS_CTRL); + writel(val | S5PCSIS_CTRL_UPDATE_SHADOW(0), base_reg + S5PCSIS_CTRL); } -- 2.34.1