From 6fb8954b08d395a831a3e98134fe6545e6293a60 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 22 Nov 2013 12:05:02 +0100 Subject: [PATCH] ARM: imx: imx53: Add SATA PHY clock Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to work correctly. Signed-off-by: Marek Vasut Cc: Richard Zhu Cc: Tejun Heo Cc: Linux-IDE Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 1 + include/dt-bindings/clock/imx5-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 07d275f..3f01df2 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -244,6 +244,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); + clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h index 5c2f634..5f2667ec 100644 --- a/include/dt-bindings/clock/imx5-clock.h +++ b/include/dt-bindings/clock/imx5-clock.h @@ -197,6 +197,7 @@ #define IMX5_CLK_SPDIF_IPG_GATE 185 #define IMX5_CLK_OCRAM 186 #define IMX5_CLK_SAHARA_IPG_GATE 187 -#define IMX5_CLK_END 188 +#define IMX5_CLK_SATA_REF 188 +#define IMX5_CLK_END 189 #endif /* __DT_BINDINGS_CLOCK_IMX5_H */ -- 2.7.4