From 6fa4fe83f723c64aba9ea0bc86c7f3e2bd07e405 Mon Sep 17 00:00:00 2001 From: Lei Liu Date: Thu, 29 Sep 2016 02:01:27 +0000 Subject: [PATCH] [AArch64] Fix test case ELF/aarch64-tls-le.s The add instruction should be generated with shift bit (lsl #12). Update the test case. llvm-svn: 282671 --- lld/test/ELF/aarch64-tls-le.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lld/test/ELF/aarch64-tls-le.s b/lld/test/ELF/aarch64-tls-le.s index 22bd0ef..23ed838 100644 --- a/lld/test/ELF/aarch64-tls-le.s +++ b/lld/test/ELF/aarch64-tls-le.s @@ -18,7 +18,7 @@ _start: #CHECK: Disassembly of section .text: #CHECK: _start: #CHECK: 11000: 40 d0 3b d5 mrs x0, TPIDR_EL0 -#CHECK: 11004: 00 00 00 91 add x0, x0, #0 +#CHECK: 11004: 00 00 40 91 add x0, x0, #0, lsl #12 #CHECK: 11008: 00 40 00 91 add x0, x0, #16 .type v1,@object -- 2.7.4